IDT77V1254L25PG IDT, Integrated Device Technology Inc, IDT77V1254L25PG Datasheet - Page 30

• Manufacturer Part Number: IDT77V1254L25PG
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT77V1254L25PG

• Data Rate: 25.6/51.2Mbps
• Number Of Channels: 4
• Type Of Atm Phy Interface: DPI/UTOPIA
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Pin Count: 144
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Counters
pated that these counters will be polled from time to time (user selectable) to evaluate performance. A separate set of registers exists for each channel
of the PHY.
Error counter and HEC Error counter were given sufficient size to indicate exact counts for low error-rate conditions. If these counters overflow, a
gross condition is occurring, where additional counter resolution does not provide additional diagnostic benefit.
Loop Timing Feature
clock. If the loop timing mode is enabled in the Enhanced Control Register 1 bit 6, the recovered receive clock is used as to clock out data on transmit
side. This mode is port specific, i.e., the user can select one or more ports to be in loop timing mode. In normal mode, the transmitter transmits data
using the multiplied oscillator clock.
IDT77V1254L25
Several condition counters are provided to assist external systems (e.g., software drivers) in evaluating communications conditions. It is antici-
The TXCell and RXCell counters are sized (16 bits) to provide a full cell count (without roll over) if the counter is read once/second. The Symbol
Reading Counters
1. Decide which counter value is desired. Write to the Counter Select Register(s) (0x06, 0x16, 0x26 and 0x36) to the bit location corresponding
2. Read the Counter Registers (0x04, 0x14, 0x24 or 0x34 (low byte)) and (0x05, 0x15, 0x25 or 0x35 (high byte)) to get the value.
Further reads may be accomplished in the same manner by writing to the Counter Select Registers.
The 77V1254L25 also offers a loop timing feature for specific applications where data needs to be repeated / transmitted using the recovered
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– 8 bits
– counts all invalid 5-bit symbols received
– 16 bits
– counts all transmitted cells
– 16 bits
– counts all received cells, excluding idle cells and HEC errored cells
– 5 bits
– counts all HEC errors received
to the desired counter. This loads the High and Low Byte Counter Registers with the selected counter’s value, and resets this counter to zero.
Transmit Cell Counters
Receive Cell Counters
Receive HEC Error Counters
Symbol Error Counters
Note: Only one counter may be enabled at any time in each of the Counter Select Registers.
Note: The PHY takes some time to set up the low and high byte counters after a specific counter has been selected in the Counter Selector
register. This time delay (in µ S) varies with the line rate and can be calculated as follows:
Time delay (µ S) =
ATM Layer Device
line rate (Mbps)
12.5___
TC sublayer
Figure 34 Line Loopback
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IDT77V1254
77V1254L25
sublayer
PMD
December 2004
Interface
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