IDT77V1254L25PG IDT, Integrated Device Technology Inc, IDT77V1254L25PG Datasheet - Page 16

• Manufacturer Part Number: IDT77V1254L25PG
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT77V1254L25PG

• Data Rate: 25.6/51.2Mbps
• Number Of Channels: 4
• Type Of Atm Phy Interface: DPI/UTOPIA
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Pin Count: 144
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

transmit data bus and a single receive data bus for data transfer.
DPI 4-bit ports, one for each of the four serial ports. As with the UTOPIA interfaces, the transmit and receive directions have their own data paths and
handshaking.
MODE[1:0] pins both low.
ATM) direction. In addition to the data bus, each direction also includes a single optional parity bit, an address bus, and several handshaking signals.
The UTOPIA address of each channel is determined by bits 4 to 0 in the Enhanced Control Registers. Please note that the transmit bus and the
receive bus operate completely independently. The Utopia 2 signals are summarized below:
(RXCLAV). To poll, the ATM device drives an address (TXADDR or RXADDR) then observes TXCLAV or RXCLAV on the next cycle of TXCLK or
RXCLK. A port must tri-state TXCLAV and RXCLAV except when it is addressed.
the address of the desired port while TXEN or RXEN is high, then driving TXEN or RXEN low. When TXEN is driven low, TXSOC (start of cell) is
driven high to indicate that the first 16 bits of the cell are being driven on TXDATA. The ATM device may chose to temporarily suspend transfer of the
cell by deasserting TXEN. Otherwise, TXEN remains asserted as the next 16 bits are driven onto TXDATA with each cycle of TXCLK.
PHY then transfers the data 16 bits each clock cycle, as determined by RXEN. As in the transmit direction, the ATM device may suspend transfer by
deasserting RXEN at any time. Note that the PHY asserts RXSOC coincident with the first 16 bits of each cell.
header and the 48-byte payload. This is shown in Figure 8.
IDT77V1254L25
Instead, key handshaking signals are duplicated so that each channel has its own signals. In both versions of UTOPIA, all channels share a single
DPI is a low-pin count Physical Layer to ATM Layer interface. The low-pin count characteristic allows the 77V1254L25 to incorporate four separate
UTOPIA Level 2 Interface option
The 16-bit Utopia Level 2 interface operates as defined in ATM Forum document af-phy-0039. This PHY-ATM interface is selected by setting the
This mode is configured as a single 16-bit data bus in the transmit (ATM-to-PHY) direction, and a single 16-bit data bus in the receive (PHY-to-
To determine if any of them has room to accept a cell for transmission (TXCLAV), or has a receive cell available to pass on to the ATM device
If TXCLAV or RXCLAV is asserted, the ATM device may select that port, then transfer a cell to or from it. Selection of a port is performed by driving
In the receive direction, the ATM device selects a port if it wished to receive the cell that the port is holding. It does this by asserting RXEN. The
TXPARITY and RXPARITY are parity bits for the corresponding 16-bit data fields. Odd parity is used.
Figure 9 through Figure 14 may be referenced for Utopia 2 bus examples.
Because this interface transfers an even number of bytes, rather than the ATM standard of 53 bytes, a filler byte is inserted between the 5-byte
UTOPIA Level 1 multi-phy interface Option
TXDATA[15:0]
TXPARITY
TXSOC
TXADDR[4:0]
TXEN
TXCLAV
TXCLK
RXDATA[15:0]
RXPARITY
RXSOC
RXADDR[4:0]
RXEN
RXCLAV
RXCLK
16 of 48
ATM to PHY
ATM to PHY
ATM to PHY
ATM to PHY
ATM to PHY
PHY to ATM
ATM to PHY
PHY to ATM
PHY to ATM
PHY to ATM
ATM to PHY
ATM to PHY
PHY to ATM
ATM to PHY
December 2004