IDT77V1054L25PF IDT, Integrated Device Technology Inc, IDT77V1054L25PF Datasheet - Page 5

• Manufacturer Part Number: IDT77V1054L25PF
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT77V1054L25PF

• Data Rate: 25.6/51.2Mbps
• Number Of Channels: 4
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 70C
• Package Type: TQFP
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

standard for 25.6Mbps ATM network communications as defined by
ATM Forum document af-phy-040.000 and ITU-T I.432.5. The physi-
cal layer is divided into a Physical Media Dependent sub layer (PMD)
and Transmission Convergence (TC) sub layer. The PMD sub layer
includes the functions for the transmitter, receiver and clock recovery
for operation across 100 meters of category 3 unshielded twisted pair
(UTP) cable. This is referred to as the Line Side Interface. The TC sub
layer defines the line coding, scrambling, data framing and synchroni-
zation.
(such as a switch core or SAR) through an 8-bit Utopia Level 2
interface.
register compatibility with it. The 77V1054, however, has additional
register features, and also duplicates most of its registers to provide
significant independence between the four ports.
IDT77V1054
Quad Port ATM PHY for 25.6 and 51.2 Mbps with 8-bit Utopia 2
The 77V1054 is a four port implementation of the physical layer
On the cell side, the 77V1054 connects to an ATM layer device
The 77V1054 is based on the 77105, and maintains significant
SIGNAL NAME
TXDATA[7:0]
TXPARITY
TXSOC
63, 62, 61, 60,
PIN NUMBER
59, 58, 57, 56
65
64
66
I/O
In
In
In
In
Utopia 2 Transmit Data. An ATM device transfers cells across this bus to the 77V1054 for
Uto pia 2 Transmit Enable. Driven by an ATM device to indicate it is transmitting data
across the TXDATA bus.
Utopia 2 Transmit Data Parity. Odd parity across TXDATA[7:0]. Parity is checked and
errors are indicated in the Interrupt Status Registers, as enabled in the Master Control
Registers. No other action is taken in the event of an error. Tie hig h or low if unused.
Utopia 2 Transmit Start of Cell. Asserted coincident with the first wo rd of data for each
cell on TXDATA.
transmission. Also see TXPARITY.
6.42
5
bus. This is an 8-bit muxed address and data bus, controlled by a
conventional asynchronous read/write handshake.
marker, and provide LED indication of receive and transmit status.
OPERATION AT 51.2 Mbps
77V1054 is also specified to operate at 51.2 Mbps. Except for the
doubled bit rate, all other aspects of operation are identical to the 25.6
Mbps mode.
OSC input pin. OSC is 32 MHz for the 25.6 Mbps line rate, and 64 MHz
for the 51.2 Mbps line rate. All ports operate at the same frequency.
Mbps operation have a higher bandwidth than magnetics optimized for
25.6 Mbps.
Access to these status and control registers is through the utility
Additional pins permit insertion and extraction of an 8kHz timing
In addition to operation at the standard rate of 25.6 Mbps, the
The rate is determined by the frequency of the clock applied to the
See page 17 for recommended line magnetics. Magnetics for 51.2
SIGNAL DESCRIPTION
Preliminary
77v1054 tbl 03