IDT77V1054L25PF IDT, Integrated Device Technology Inc, IDT77V1054L25PF Datasheet - Page 10

• Manufacturer Part Number: IDT77V1054L25PF
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT77V1054L25PF

• Data Rate: 25.6/51.2Mbps
• Number Of Channels: 4
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 70C
• Package Type: TQFP
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

by the ATM Forum. It transfers ATM cells and has separate transmit
and receive channels and specific handshaking protocols. UTOPIA
Level 2 has dedicated address signals for both the transmit and
receive directions that allow the ATM layer device to specify with which
of the four PHY channels it is communicating. It is defined in ATM
Forum document af-phy-0039.
and 1 Rx Clav" multi-phy scheme. The optional Direct Status
Indication and Multiplexed Status Polling multi-phy schemes are not
directly supported.
direction, and a single 8-bit data bus in the receive (PHY-to-ATM)
direction. In addition to the data bus, each direction also includes a
single optional parity bit, an address bus, and several handshaking
signals. The UTOPIA address of each channel is determined by bits
4 to 0 in the Enhanced Control Registers. Please note that the transmit
bus and the receive bus operate completely independently. The
Utopia signals are summarized below:
IDT77V1054
Quad Port ATM PHY for 25.6 and 51.2 Mbps with 8-bit Utopia 2
UTOPIA is a Physical Layer to ATM Layer interface standardized
Note that the 77V1054 supports only the "Operation with 1 TxClav
There is a single 8-bit data bus in the transmit (ATM-to-PHY)
TXDATA[7:0]
TXPARITY
TXSOC
TXADDR[4:0]
TXEN
TXCLAV
TXCLK
RXDATA[7:0]
RXPARITY
RXSOC
RXADDR[4:0]
RXEN
RXCLAV
RXCLK
ATM to PHY
ATM to PHY
ATM to PHY
ATM to PHY
ATM to PHY
PHY to ATM
ATM to PHY
PHY to ATM
PHY to ATM
PHY to ATM
ATM to PHY
ATM to PHY
PHY to ATM
ATM to PHY
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to determine if any of them has room to accept a cell for transmission
(TXCLAV), or has a receive cell available to pass on to the ATM device
(RXCLAV). To poll, the ATM device drives an address (TXADDR or
RXADDR) then observes TXCLAV or RXCLAV on the next cycle of
TXCLK or RXCLK. A port must tri-state TXCLAV and RXCLAV except
when it is addressed.
port, then transfer a cell to or from it. Selection of a port is performed
by driving the address of the desired port while TXEN or RXEN is high,
then driving TXEN or RXEN low. When TXEN is driven low, TXSOC
(start of cell) is driven high to indicate that the first byte of the cell are
being driven on TXDATA. The ATM device may chose to temporarily
suspend transfer of the cell by deasserting TXEN. Otherwise, TXEN
remains asserted as the next byte is driven onto TXDATA with each
cycle of TXCLK.
to receive the cell that the port is holding. It does this by asserting
RXEN. The PHY then transfers the data 8 bits each clock cycle, as
determined by RXEN. As in the transmit direction, the ATM device may
suspend transfer by deasserting RXEN at any time. Note that the PHY
asserts RXSOC coincident with the first byte of each cell.
bit data fields. Odd parity is used.
examples.
The ATM device starts by polling the PHY ports on the Utopia bus
If TXCLAV or RXCLAV is asserted, the ATM device may select that
In the receive direction, the ATM device selects a port if it wished
TXPARITY and RXPARITY are parity bits for the corresponding 8-
The following figures may be referenced for Utopia Level 2 bus
Preliminary