IDT77V1054L25PF IDT, Integrated Device Technology Inc, IDT77V1054L25PF Datasheet - Page 18

• Manufacturer Part Number: IDT77V1054L25PF
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT77V1054L25PF

• Data Rate: 25.6/51.2Mbps
• Number Of Channels: 4
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 70C
• Package Type: TQFP
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

The 77V1054 has 37 registers that are accessible through the utility bus. Each of the four ports has 9 registers dedicated to that port. There is only one
register (0x40) which is not port specific.
For those register bits which control operation of the Utopia interface, the operation of the Utopia interface is determined by the registers corresponding to
the port which is selected at that particular time. For consistent operation, the Utopia control bits should be programmed the same for all four ports, except
for the Utopia 2 port addresses in the Enhanced Control Registers.
Nomenclature
"Reserved" register bits, if written, should always be written "0"
R/W = register may be read and written via the utility bus
R-only or W-only = register is read-only or write-only
sticky = register bit is cleared after the register containing it is read; all sticky bits are read-only
“0” = ‘cleared’ or ‘not set’
“1” = ‘set’
Master Control Registers
Interrupt Status Registers
Diagnostic Control Registers
LED Driver and HEC Status/control
Low Byte Counter Register [7:0]
High Byte Counter Register [15:8]
Counter Registers Read Select
Interrupt Mask Registers
Enhanced Control Registers
Addresses: 0x00, 0x10, 0x20, 0x30
IDT77V1054
Quad Port ATM PHY for 25.6 and 51.2 Mbps with 8-bit Utopia 2
Bit
7
6
5
4
3
2
0
1
and
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Control Register
0 = all interrupts Enable Cell Error Interrupts Only
Register Name
0 = not halted
errored cells
0 = disabled
Initial State
1 = discard
1 = discard
1 = enable
idle cells
interrupts
0
0
Reserved
Discard Receive Error Cells
On receipt of any cell with an error (e.g. short cell, invalid command mnemonic, receive HEC error
(if enabled)), this cell will be discarded adn will not enter the receive FIFO.
If Bit 0 in this register is set (Interrupts Enabled), setting of this bit enables only "Received Cell Error"
(as defined in bit 6) to trigger interrupt line.
Directs TC to check parity of TxDATA against parity bit located in TXPARITY.
Discard Received Idle Cells
Directs TC to discard received idle (VPI/VCI = 0) cells from PMD without signalling external systems.
Halt Tx
Halts transmission of data from TC to PMD and forces the TxD outputs to the "0" state.
Reserved
Enable Interrupt Pin (Interrupt Mask Bit)
Enables interrupt output pin (pin 108). If cleared, pin is always high and interrupt is masked. If set, an
interrupt will be signaled by setting the interrupt pin to "0". It doesn't affect the Interrupt Status Registers.
Transmit Data Parity Check
Port 0
0x00
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x01
18
Port 1
0x10
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x11
Function
Register Address
Port 2
0x20
0x22
0x23
0x24
0x25
0x26
0x27
0x28
0x21
Port 3
0x30
0x32
0x33
0x34
0x35
0x36
0x37
0x38
0x31
All Ports
Preliminary
0x40
77v1054 tbl 15
3505 tbl 14