ETC5064N/C STMicroelectronics, ETC5064N/C Datasheet - Page 3

• Manufacturer Part Number: ETC5064N/C
• Description: RF Wireless Misc Interfc CODEC Filter
• Manufacturer: STMicroelectronics
• Type: Telecom IC'sr

Specifications of ETC5064N/C

• Operating Frequency: 2.048 MHz
• Operating Temperature Range: - 25 C to + 125 C
• Package / Case: DIP-20
• Mounting Style: Through Hole
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIN DESCRIPTION
(*) I: Input, O: Output, S: Power Supply.
TRI-STATE
BCLK
MCKL
MCLK
BCLK
GNDA
Name
ANLB
VPO
VF
VF
VPO
VF
R
GS
V
FS
FS
TS
VPI
V
D
D
/CLKSEL
CC
BB
R
R
X
R
X
X
R
X
X
/PDN
X
O
I
I
+
+
is a trademark of National Semiconductor Corp.
-
-
X
X
Type (*)
GND
Pin
O
O
O
O
O
O
S
S
I
I
I
I
I
I
I
I
I
I
I
10
11
12
13
14
15
16
17
18
19
20
N
1
2
3
4
5
6
7
8
9
The Non-inverting Output of the Receive Power Amplifier
Analog Ground. All signals are referenced to this pin.
The Inverting Output of the Receive Power Amplifier
Inverting Input to the Receive Power Amplifier. Also powers down both
amplifiers when connected to V
Analog Output of the Receive Filter.
Positive Power Supply Pin. V
Receive Frame Sync Pulse which enable BCLK
D
Receive Data Input. PCM data is shifted into D
edge
The bit Clock which shifts data into D
vary from 64KHz to 2.048MHz.
Alternatively, may be a logic input which selects either 1.536MHz/1.544MHz
or 2.048MHz for master clock in synchronous mode and BCLK
for both transmit and receive directions (see table 1). This input has an
internal pull-up.
Receive Master Clock. Must be 1.536MHz, 1.544MHz or 2.048MHz. May
be asynchronous with MCLK
best performance. When MCLK
selected for all internal timing. When MCLK
high, the device is powered down.
Transmit Master Clock. Must be 1.536MHz, 1.544MHz or 2.048MHz. May
be asynchronous with MCLK
The bit clock which shifts out the PCM data on D
to 2.048MHz, but must be synchronous with MCLK
The TRI-STATE PCM data output which is enabled by FS
Transmit frame sync pulse input which enables BCLK
PCM data on D
timing details.
Open drain output which pulses low during the encoder time slot. Must to
be grounded if not used.
Analog Loopback Control Input. Must be set to logic ’0’ for normal
operation. When pulled to logic ’1’, the transmit filter input is disconnected
from the output of the transmit preamplifier and connected to the VPO
output of the receive power amplifier.
Analog output of the transmit input amplifier. Used to set gain externally.
Inverting input of the transmit input amplifier.
Non-inverting input of the transmit input amplifier.
Negative Power Supply Pin. V
R
. FS
R
is an 8KHz pulse train. See figures 1 and 2 for timing details.
ETC5064 - ETC5064-X - ETC5067 - ETC5067-X
X
. FS
X
is an 8KHz pulse train. See figures 1 and 2 for
X
R
CC
, but should be synchronous with MCLK
.
BB
BB
Description
R
= +5V 5%
= -5V 5%
is connected continuously low, MCLK
.
R
after the FS
R
is connected continuously
R
R
following the FS
X
to shift PCM data into
. May vary from 64KHz
R
X
.
leading edge. May
X
to shift out the
X
.
X
is used
R
leading
X
+
X
for
3/18
is