ETC5064 STMicroelectronics, ETC5064 Datasheet
ETC5064
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ETC5064 Summary of contents
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... OPERATION: ETC5064/67 – OPERATION: ETC5064-X/67-X DESCRIPTION The ETC5064 ( -law), ETC5067 (A-law) are mono- lithic PCM CODEC/FILTERS utilizing the A/D and D/A conversion architectureshown in the Block Dia- grams and a serial PCM interface. The devices are fabricated using double-poly CMOS process. ...
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... ETC5064 - ETC5064-X - ETC5067 - ETC5067-X PIN CONNECTIONS (Top views) DIP20 & SO20 BLOCK DIAGRAM (ETC5064 - ETC5064-X - ETC5067 - ETC5067-X) 2/18 PLCC20 ...
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... BB (*) I: Input, O: Output, S: Power Supply. TRI-STATE is a trademark of National Semiconductor Corp. ETC5064 - ETC5064-X - ETC5067 - ETC5067-X Description The Non-inverting Output of the Receive Power Amplifier Analog Ground. All signals are referenced to this pin. The Inverting Output of the Receive Power Amplifier Inverting Input to the Receive Power Amplifier. Also powers down both amplifiers when connected to V ...
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... X R receive clocks may be applied. MCLK must be 2.048 MHz for the ETC5067 or 1.536 MHz, pulse. The X 1.544 MHz for the ETC5064, and need not be syn- chronous. For best transmission performance, how- pulse. X ever, MCLK should be synchronouswith MCLK R which is easily achieved by applyingonly static logic ...
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... X pass filter clocked at 256kHz. The decoder is A-law (ETC5067 and ETC5067-X) or –law (ETC5064 and ETC5064-X) and the 5 th order low pass filter corrects for the sin x/x attenuation due to the 8kHz sample and hold. The filter is then followed order RC active post-filter and power amplifier capable of driving a 600 load to a level of 7 ...
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... ANALOG INTERFACE WITH RECEIVE FILTER (all devices) Symbol R RF Output Resistance Load Resistance ( Load Capacitance L VOS O Output DC Offset Voltage R 6/ to70 C (ETC5064-X/67- 5.0V, V =-5.0V Parameter )all digital inputs Except ANLB ...
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... POWER DISSIPATION (all devices) Symbol I 0 Power-down Current at ETC6064/ Power-down Current at ETC6064/ Active Current at ETC6064/67 CC ETC5064-X/67 Active Current at ETC6064/67 BB ETC5064-X/67-X ETC5064 - ETC5064-X - ETC5067 - ETC5067-X Parameter VPI 1.0 V) VPI 1 – or VPO ) – – or VPO to GNDA) – Vrms ...
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... ETC5064 - ETC5064-X - ETC5067 - ETC5067-X All TIMING SPECIFICATIONS Symbol 1/t Frequency of master clocks PM MCLK and MCLK X R Depends on the device used and the BCLK /CLKSEL Pin R t Width of Master Clock High WMH t Width of Master Clock Low WML t Rise Time of Master Clock RM t Fall Time of Master Clock ...
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... Figure 2 : Short Frame Sync Timing. ETC5064 - ETC5064-X - ETC5067 - ETC5067-X 9/18 ...
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... ETC5064 - ETC5064-X - ETC5067 - ETC5067-X Figure 3 : Long Frame Sync Timing. 10/18 ...
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... TRANSMISSION CHARACTERISTICS (all devices (ETC5064-X/67- GNDA = 0V 1.02kHz 0dBm0 transmit input amplifier connected forunity–gainnon–inverting.(unless IN otherwise specified). AMPLITUDE RESPONSE Symbo l Absolute Levels - Nominal 0 dBm0 is 4 dBm (600 ). 0 dBm0 t Max Overload Level MAX 3.14 dBm0 3.17 dBm0 G Transmit Gain, Absolute (T ...
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... ETC5064 - ETC5064-X - ETC5067 - ETC5067-X TRANSMISSION CHARACTERISTICS (continued). ENVELOPE DELAY DISTORTION WITH FREQUENCY Symbol D Transmit Delay, Absolute (f = 1600 Hz Transmit Delay, Relative 500 Hz-600 600 Hz-800 800 Hz-1000 1000 Hz-1600 1600 Hz-2600Hz f = 2600 Hz-2800 2800 Hz-3000 Hz ...
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... PPSRX, NPSRX, CTR–X measured with a –50dBm0 activating signal applied at VF ENCODING FORMAT AT D OUTPUT Full-scale ( ( – Full-scale IN X ETC5064 - ETC5064-X - ETC5067 - ETC5067-X Parameter XMT RCV XMT RCV = – 4 dBm0 to X Parameter = Steady PCM Code ETC5064/67 ETC5064-X/67 ...
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... ETC5064 - ETC5064-X - ETC5067 - ETC5067-X APPLICATION INFORMATION POWER SUPPLIES While the pins at the ETC506X family are well pro- tected against electrical misure recommended that the standard CMOS practice be followed, en- suring that ground is connected to the device before any other connections are made. In applications where the printed circuit board may be plugged into a ” ...
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... SO20 PACKAGE MECHANICAL DATA DIM. MIN 0 0. 7 ETC5064 - ETC5064-X - ETC5067 - ETC5067-X mm TYP. MAX. MIN. 2.65 0.2 0.004 2.45 0.49 0.014 0.32 0.009 0.5 45 (typ.) 13.0 0.496 10.65 0.394 1.27 11.43 7.6 0.291 1.27 0.020 0.75 8 (max.) inch TYP. MAX. 0.104 0.008 0.096 0.019 0.013 0.020 0.510 0.419 ...
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... ETC5064 - ETC5064-X - ETC5067 - ETC5067-X PLCC20 PACKAGE MECHANICAL DATA DIM. MIN. A 9.78 B 8. 16/18 mm TYP. MAX. MIN. 10.03 0.385 9.04 0.350 4.57 0.165 2.54 0.56 8.38 0.290 1.27 5.08 0.38 0.101 1.27 1.14 inch TYP. MAX. 0.395 0.356 0.180 0.100 0.022 0.330 0.050 0.200 0.015 0.004 0.050 0.045 ...
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... DIP20 PACKAGE MECHANICAL DATA DIM. MIN. a1 0.254 B 1. ETC5064 - ETC5064-X - ETC5067 - ETC5067-X mm TYP. MAX. MIN. 0.010 1.65 0.055 0.45 0.25 25.4 8.5 2.54 22.86 7.1 3.93 3.3 1.34 inch TYP. MAX. 0.065 0.018 0.010 1.000 0.335 0.100 0.900 0.280 0.155 0.130 0.053 17/18 ...
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... ETC5064 - ETC5064-X - ETC5067 - ETC5067-X Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifica- tions mentioned in this publication are subject to change without notice ...