MT48LC8M16A2P-75:G TR Micron Technology Inc, MT48LC8M16A2P-75:G TR Datasheet - Page 63

DRAM Chip SDRAM 128M-Bit 8Mx16 3.3V 54-Pin TSOP-II T/R

MT48LC8M16A2P-75:G TR

Manufacturer Part Number
MT48LC8M16A2P-75:G TR
Description
DRAM Chip SDRAM 128M-Bit 8Mx16 3.3V 54-Pin TSOP-II T/R
Manufacturer
Micron Technology Inc
Type
SDRAMr
Datasheet

Specifications of MT48LC8M16A2P-75:G TR

Package
54TSOP-II
Density
128 Mb
Address Bus Width
14 Bit
Operating Supply Voltage
3.3 V
Maximum Clock Rate
133 MHz
Maximum Random Access Time
6|5.4 ns
Operating Temperature
0 to 70 °C
Format - Memory
RAM
Memory Type
SDRAM
Memory Size
128M (8Mx16)
Speed
133MHz
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Package / Case
54-TSOP II
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
557-1217-2
MT48LC8M16A2P-75:G TR
Figure 47:
PDF: 09005aef8091e66d/Source: 09005aef8091e625
128MSDRAM_2.fm - Rev. N 1/09 EN
DQML, DQMH
A0–A9, A11
COMMAND
BA0, BA1
DQM /
CKE
CLK
A10
DQ
t CKS
t CMS
t AS
t AS
t AS
ACTIVE
BANK
T0
ROW
ROW
READ – Full-Page Burst
t CKH
t CMH
t AH
t AH
t AH
t RCD
Notes:
t CL
T1
NOP
t CH
1. For this example, CL = 2.
2. x16: A9 and A11 = “Don’t Care.”
3. Page left open; no
t CMS
x8: A11 = “Don’t Care.”
t CK
COLUMN m 2
T2
BANK
READ
t CMH
CAS Latency
T3
NOP
t LZ
t AC
t
RP.
T4
D
NOP
OUT
t OH
1,024 (x8) locations within same row
2,048 (x4) locations within same row
m
63
t AC
512 (x16) locations within same row
Full-page burst does not self-terminate.
Can use BURST TERMINATE command.
D
T5
OUT
NOP
t OH
m+1
Full page completed
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t AC
D
T6
OUT
NOP
t OH
t AC
m+2
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128Mb: x4, x8, x16 SDRAM
Tn + 1
D
NOP
OUT
t OH
m-1
t AC
©1999 Micron Technology, Inc. All rights reserved.
BURST TERM
Tn + 2
3
D
Timing Diagrams
OUT
t OH
m
t AC
Tn + 3
D
OUT
NOP
t OH
m+1
t HZ
DON’T CARE
UNDEFINED
Tn + 4
NOP

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