CS42526-CQZR Cirrus Logic Inc, CS42526-CQZR Datasheet - Page 51

• Manufacturer Part Number: CS42526-CQZR
• Description: Audio CODECs IC 114dB 192kHz 6Ch Mlt-Ch CODEC
• Manufacturer: Cirrus Logic Inc

Specifications of CS42526-CQZR

• Number Of Adc Inputs: 2
• Number Of Dac Outputs: 6
• Conversion Rate: 192 KSPs
• Interface Type: Serial (SPI)
• Resolution: 24 bit
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-64
• Minimum Operating Temperature: - 10 C
• Number Of Channels: 2 ADC, 6 DAC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DS585F1
6.5.4
6.5.5
6.6
6.6.1
6.6.2
6.6.3
Ext ADC SCLK
7
SAI RIGHT-JUSTIFIED BITS (SAI_RJ16)
CODEC RIGHT-JUSTIFIED BITS (CODEC_RJ16)
Misc Control (address 05h)
EXTERNAL ADC SCLK SELECT (EXT ADC SCLK)
RMCK HIGH IMPEDANCE (HIZ_RMCK)
FREEZE CONTROLS (FREEZE)
Default = 0
Function:
Default = 0
Function:
Default = 0
Function:
Default = 0
Function:
Default = 0
Function:
This bit determines how many bits to use during right-justified mode for the Serial Audio Interface
Port. By default the receiver will be in RJ24 bits but can be set to RJ16 bits.
0 - 24 bit mode.
1 - 16 bit mode.
This bit determines how many bits to use during Right-Justified Mode for the DAC and ADC within
the CODEC Serial Port. By default, the DAC and ADC will be in RJ24 bits, but can be set to RJ16 bits.
0 - 24 bit mode.
1 - 16 bit mode.
This bit identifies the SCLK source for the external ADCs attached to the ADCIN1/2 ports when using
One-Line Mode of operation.
0 - SAI_SCLK is used as external ADC SCLK.
1 - CX_SCLK is used as external ADC SCLK.
This bit is used to create a high-impedance output on RMCK when the clock signal is not required.
This function will freeze the previous output of, and allow modifications to be made to, the Volume
Control (address 0Fh-16h), Channel Invert (address 17h), and Mixing Control Pair (address 18h-1Bh)
registers without the changes taking effect until the FREEZE is disabled. To make multiple changes
in these control port registers take effect simultaneously, enable the FREEZE bit, make all register
changes, then disable the FREEZE bit.
HiZ_RMCK
6
Reserved
5
FREEZE
4
FILT_SEL
3
HPF_FREEZE CODEC_SP
2
M/S
1
CS42526
SAI_SP
M/S
0
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