CYII5SM1300AB-QDC Cypress Semiconductor Corp, CYII5SM1300AB-QDC Datasheet - Page 5

• Manufacturer Part Number: CYII5SM1300AB-QDC
• Description: SENSOR IMAGE MONO CMOS 84-LCC
• Manufacturer: Cypress Semiconductor Corp
• Type: CMOS Imagingr

Specifications of CYII5SM1300AB-QDC

• Pixel Size: 6.7µm x 6.7µm
• Active Pixel Array: 1280H x 1024V
• Frames Per Second: 27
• Voltage - Supply: 3 V ~ 4.5 V
• Package / Case: 84-LCC
• Sensor Image Color Type: Monochrome
• Sensor Image Size Range: >= 480,000Pixels
• Sensor Image Size: 1280x1024Pixels
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 65C
• Package Type: CLCC
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 84
• Package: 84CLCC
• Image Size: 1280x1024 Pixels
• Color Sensing: Monochrome
• Operating Temperature: 0 to 65 °C
• Operating Supply Voltage: 3 to 3.6 V
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Architecture and Operation
This section presents detailed information about the most important sensor blocks
Floor Plan
Figure 2
sensor. It consists basically of a pixel array, one X- and two
Y-addressing registers for the readout in X- and Y-direction,
column amplifiers that correct for the fixed pattern noise, an
analog multiplexer, and an analog output amplifier.
Use the left Y-addressing register for readout operation. Use the
right Y-addressing register for reset of pixel rows. In multiple
slope synchronous shutter mode, the right Y-addressing register
resets the whole pixel core with a lowered reset voltage. In rolling
Document #: 38-05710 Rev. *H
shows the architecture of the IBIS5-B-1300 image
addressing
Y-left
Figure 2. Block Diagram of IBIS5-B-1300 Image Sensor
Pixel
Column amplifiers
X-addressing
Analog multiplexer
Pixel core
Imager core
Y-right
addressing
Output
amplifier
curtain shutter mode, use the right Y-addressing register for the
reset pointer in single and double slope operation to reset one
pixel row.
The on-chip sequencer generates most of the signals for the
image core. Some basic signals (such as start/stop integration,
line and frame sync signals) are generated externally.
A 10-bit ADC is implemented on chip but electrically isolated
from the image core. You must route the analog pixel output to
the analog ADC input on the outside.
ADC
Sequencer
Sensor
System clock
40 MHz
External
connection
Sample
Reset
C
Column output
CYII5SM1300AB
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