CYII5SM1300AB-QDC Cypress Semiconductor Corp, CYII5SM1300AB-QDC Datasheet
CYII5SM1300AB-QDC
Specifications of CYII5SM1300AB-QDC
Related parts for CYII5SM1300AB-QDC
CYII5SM1300AB-QDC Summary of contents
Page 1
... Traffic monitoring ■ Ordering Information See Ordering Code Information on page 33 for more information. Marketing Part Number CYII5SM1300AB-QDC CYII5SM1300AB-QWC CYII5SC1300AB-QDC CYII5FM1300AB-QDC Cypress Semiconductor Corporation Document #: 38-05710 Rev. *H IBIS5 1.3 Megapixel CMOS Image Sensor Description The IBIS5-B-1300 is a solid state CMOS image sensor that integrates the functionality of complete analog image acquisition, digitizer, and digital signal processing system on a single chip ...
Page 2
... Analog-to-Digital Converter ............................................ 13 Electronic Shutter Types ................................................ 15 Sequencer ...................................................................... 15 Timing Diagrams ................................................................. 20 Frame Rate .................................................................... 20 Timing Requirements ..................................................... 20 Global Shutter: Single Slope Integration ........................ 21 Document #: 38-05710 Rev. *H CYII5SM1300AB Global Shutter: Pixel Readout ........................................ 22 Global Shutter: Multiple Slope Integration ...................... 23 Rolling Shutter Operation ............................................... 24 Windowing in X-Direction ............................................... 24 Windowing in Y-Direction ............................................... 25 Initialization (Startup Behavior) ...................................... 25 Package Information ........................................................... 26 Pin List ...
Page 3
... Parameter Sensitivity Full Well Charge Temporal Noise Parasitic light sensitivity Dark noise Signal to Noise Ratio Fixed pattern noise (FPN) 4.5 LSB10 Dark signal [2] Description Description CYII5SM1300AB Specifications 8.4 V/lux.s at 650 nm - 62500 e 2.5 LSB10 3% - 21e 64 dB 5.5 LSB10/sec at 30 °C Min Max Units ° ...
Page 4
... N/A +3.0 34.5 mA N/A N/A 10.5 mA N/A N/A N/A N/A 0 Condition V = VDD or GND IN VDD = min –100 µA OH VDD = min 100 µA OH System clock <= 40 MHz CYII5SM1300AB Typ Max Unit +4.5 +4.5 V +4.5 +4.5 V +3.0 +3.3 V +3.3 +3.6 V +3.3 +3.6 V N/A N/A mA ...
Page 5
... Some basic signals (such as start/stop integration, line and frame sync signals) are generated externally. A 10-bit ADC is implemented on chip but electrically isolated from the image core. You must route the analog pixel output to the analog ADC input on the outside. CYII5SM1300AB Reset C Select Sample ...
Page 6
... Note that this response curve includes the optical cross talk of the pixels. Figure 4. Color Filter Arrangement of Pixels R G1 (0,0) Figure 5. Spectral Response for IBIS5-B-Color CYII5SM1300AB Figure 5 shows the response of the color G2 B Page [+] Feedback ...
Page 7
... Figure 6 shows the spectral response characteristic for the IBIS5-B-1300 (CYII5SM1300AB) and the IBIS-5-BE-1300 (CYII5FM1300AB). The curve is measured directly on the pixels. It includes effects of non-sensitive areas in the pixel, for example, interconnection lines. The sensor is light sensitive between 400 and 1000 nm. The peak QE × 30%, approximately around 650 nm ...
Page 8
... The resulting image sharpness is hardly affected by this decreased MTF value. Both IBIS5-B-1300 versions are fully pin compatible and have identical timing and biasing Document #: 38-05710 Rev. *H Figure 7. Electro-Voltaic Response Curve 20000 30000 40000 50000 60000 # electrons IBIS5-BE-1300 0.37 0.18 0.16 0.07 0.26 0.16 0.13 0.11 CYII5SM1300AB 70000 80000 Figure 6 on page 7. As many Page [+] Feedback ...
Page 9
... The pixel array (VDDR_LEFT, VDDH and VDDC) analog supplies are especially vulnerable to this. Figure 8. Image Core SAMPLE RESET HOLD Pixel row Pixel Pixel A B Pixel column Column amplifiers Read-pointer X addressing CYII5SM1300AB Vddreset VDDR_RIGHT Y-right addressing Y_START Y_CLOCK VDDC Output amplifier PXL_OUT Page [+] Feedback ...
Page 10
... Each biasing signal determines the operation of a corresponding module in the sense that it controls the speed and power dissi- pation. The tolerance on the DC-level of the bias levels can vary ±150 mV due to process variations. Comment CYII5SM1300AB Table 9 to achieve the best possible Description Typ Voltage on HOLD switches ...
Page 11
... Activating Y_SWAP12 results in pattern ’XOXOXOXO’. Activating Y_SWAP30 results in pattern ’OXOXOXOX’. Activating both Y_SWAP12 and Y_SWAP30 results in pattern ’OOXXOOXX’. The addressable pixel range when Y-sub sampling is enabled is: 0–1, 4–5, 8–9, 12–13, … 1020–1021 CYII5SM1300AB Y_SWAP12 Y_SWAP30 Reg(n) Reg(n+1) SRH ...
Page 12
... DAC_VLOW. The range of the DAC is defined using a resistive division with R Figure 12. Internal and External ADC Connections 3. The internal resistor R The recommend resistor values for both DAC_VLOW and DAC_VHIGH are 0 Ω. CYII5SM1300AB Amplifier Register (6:0) Table DC Gain Bits DC Gain 1.37 1000 6 ...
Page 13
... DARK_ANALOG ADC_VLOW). The values of the resistors depend on the value of R assure proper working of the ADC, make certain the voltage difference between ADC_VLOW and ADC_VHIGH is at least 1.0 V. CYII5SM1300AB Figure 13 shows this pipeline delay. has a value of approximately 585 Ω. Value (O) 360 585 ...
Page 14
... ADC output value. 3. Change DAC_FINE such that the average of the odd columns is almost same as the even columns. 4. Change DAC_RAW again such that all pixels have a non-zero output, but are as close to zero as possible. 5. Repeat for different gains. CYII5SM1300AB Page [+] Feedback ...
Page 15
... On power-on, all registers in the sensor are reset to zero. To start operating the sensor, first load all the registers using the parallel or serial-3-wire interface. The value to be loaded in each register on power-on is given in the table. CYII5SM1300AB Common Sample & Hold Time Burst ...
Page 16
... Swap columns 1-2, 5-6, … Swap columns 3-4, 7-8, … Enable sub-sampling in Y-direction Swap rows 1-2, 5-6, … Swap rows 3-4, 7-8, … Default value <6:0>: ’1010000’ Output amplifier gain setting 1 = Amplifier in unity gain mode 1 = Activates second output 0 = Amplifier in standby mode CYII5SM1300AB Page [+] Feedback ...
Page 17
... In normal (single slope) mode the pixel reset is controlled from the left side of the image core using the voltage applied on pin VDDR_LEFT as pixel reset voltage. In multiple slope opera- tion, apply one or more variable pixel reset voltages. CYII5SM1300AB (bit 7) and SS-Sequencer ...
Page 18
... Treg_int Difference between the left and right pointer = value set in the INT_TIME register (number of lines). The actual integration time is given by Tint Integration time [# lines] = NROF_LINES register – INT_TIME register. Tint Integration time [# lines] = NROF_LINES register – INT_TIME register lin llo ift ift CYII5SM1300AB Internal clock on page 17). Figure 18 Page [+] Feedback ...
Page 19
... IBIS5-B-1300. The maximum tested frequency of S_DATA is 2.5 MHz.) Serial 2-Wire Interface The serial 2-wire interface is not operational in the IBIS5-B-1300 image sensor. Use the 3-wire SPI interface to load the sensor registers. Figure 19. Parallel Interface Timing CYII5SM1300AB Output Amplifier on SER_MODE Selected interface X Parallel ...
Page 20
... MHz pixel rate) with an integration time of 1 ms: Frame period = (1024 × (3.5 µ × 1280 26.8 fps Document #: 38-05710 Rev. *H CYII5SM1300AB Region-of-Interest (ROI) Read Out Windowing is easily achieved by uploading the starting point of the X- and Y-shift registers in the sensor registers using the various interfaces ...
Page 21
... SS-sequencer clock periods. The integration Figure 22). time counter starts counting at the first rising edge after the falling edge of SS_START The SS-sequencer puts the image core in a readable state takes two granulated SS-sequencer clock periods The ’real’ integration or exposure time. int CYII5SM1300AB Page [+] Feedback ...
Page 22
... The application note discusses the cause and corrective action for this problem. Figure 23. Global Shutter: Pixel Read Out Table 21. Row Blanking Time as Function of X-Sequencer Granularity Granularity N GRAN × 4 × 8 × 16 × 32 Figure 24. Pixel Output CYII5SM1300AB AN6004, T (µs) GRAN_X_SEQ × N × T MSB/LSB GRAN SYS_CLOCK 140 × 3.5 ...
Page 23
... T T depends on the interface mode used to upload the upload registers. Table 24. T for Different Interface Modes upload Enable Interface Mode 0 Parallel 1 Serial 3-wire CYII5SM1300AB , otherwise, the change stable stable T (µs) GRAN_SS_SEQ stable × T MSB/LSB GRAN SYS_CLOCK = 4 00 SYS_CLOCK = 8 01 SYS_CLOCK ...
Page 24
... Interface Mode Parallel interface Serial 3 Wire The actual time to load the register itself depends on the interface mode that is used. The parallel interface is the fastest. Figure 26. Rolling Shutter Operation Figure 27. Windowing in X-Direction CYII5SM1300AB ; it is defined load T (µs) load 1 (about 40 SYS_CLOCK cycles) 16 (at 2.5 MHz data rate) ...
Page 25
... All internal registers are set to ‘0’ after SYS_RESET is applied. Because all the IBIS5-B-1300 control signals are active high, apply a low level (before SYS_RESET occurs) to these pins at start up to avoid latch up. Figure 28. Windowing in Y-Direction CYII5SM1300AB Page [+] Feedback ...
Page 26
... You can connect all pins with the same name together. 9. All digital input are active high (unless mentioned otherwise). 10. Tie all digital inputs that are not used to GND (inactive level). Document #: 38-05710 Rev. *H CYII5SM1300AB Table 26 lists the pins and Pin Description ...
Page 27
... Digital output. ADC data output. 61 ADC_OUT<7> Output Digital output. ADC data output. 62 ADC_OUT<6> Output Digital output. ADC data output. 63 ADC_OUT<5> Output Digital output. ADC data output. 64 ADC_OUT<4> Output Digital output. ADC data output. Document #: 38-05710 Rev. *H CYII5SM1300AB Pin Description Page [+] Feedback ...
Page 28
... Digital input. Data parallel interface. 81 P_DATA<12> Input Digital input. Data parallel interface. 82 P_DATA<11> Input Digital input. Data parallel interface. 83 P_DATA<10> Input Digital input. Data parallel interface. 84 P_DATA<9> Input Digital input. Data parallel interface. Document #: 38-05710 Rev. *H CYII5SM1300AB Pin Description Page [+] Feedback ...
Page 29
... Scribe lines take about 100 to 150 µm extra on each side. Pin 1 is located in the middle of the left side, indicated by a ‘1’ on the layout. A logo and some identification tags are on the top right of the die. Figure 29. IBIS5-B-1300 Bare Die Dimensions (All dimensions in µm) Test structure Document #: 38-05710 Rev. *H CYII5SM1300AB Identification Page [+] Feedback ...
Page 30
... Package Drawing with Glass Document #: 38-05710 Rev. *H CYII5SM1300AB 001-07589 *A Page [+] Feedback ...
Page 31
... Description Figure 31) Figure 30. Side View Dimensions CYII5SM1300AB Package Drawing with Glass on page 30) Max 0.600 1.980 – – 0.090 0.110 – – 1.330 Min Typ Max Units NA 0.740 ...
Page 32
... Document #: 38-05710 Rev. *H CYII5SM1300AB Figure 31 shows the transmission characteristics of the glass RoHS (Pb-free) Compliance This paragraph reports the use of hazardous chemical substances as required by the RoHS Directive (excluding packing material) ...
Page 33
... The Cypress Video Capture software (provided in the CD with reference schematics) is compatible with Windows-XP operating system and allows to grab live images from the sensor, store the images in different formats for analysis and test different functional modes of the sensor Figure 32. The IBIS5 Demo Kit CYII5SM1300AB Page [+] Feedback ...
Page 34
... Document History Page Document Title: CYII5SM1300AB IBIS5 1.3 Megapixel CMOS Image Sensor Document Number: 38-05710 Orig. of Rev. ECN No. Change ** 310213 FVK *A 649064 FPW *B 1162847 FPW/ARI *C 1417584 FPW *D 2765859 NVEA *E 2786518 SHEA *F 2903130 NVEA *G 3056594 NVEA *H 3137684 NVEA Document #: 38-05710 Rev. *H Submission ...
Page 35
... Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 38-05710 Rev. *H All products and company names mentioned in this document may be the trademarks of their respective holders. Revised January 13, 2011 CYII5SM1300AB Page [+] Feedback ...