CYII4SM014KAA-GECU Cypress Semiconductor Corp, CYII4SM014KAA-GECU Datasheet - Page 6

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CYII4SM014KAA-GECU

Manufacturer Part Number
CYII4SM014KAA-GECU
Description
IC IMAGE SENSOR 14MP CMOS 49-PGA
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of CYII4SM014KAA-GECU

Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Figure 3. Location of 24 Additional Columns and Rows, Scan
Direction of the Array
Pixel Specifications
The pixel is a classic three transistor active pixel. The photodiode
is a high-fill-factor n-well/p-substrate diode. The chip has
separate power supplies for the following:
Separate power supply for the pixel itself (VDDARRAY).
Figure 4. Pixel and Column Structure Schematic
Document #: 38-05709 Rev. *F
RESET
24 x 4536 dummy pixels
General power supply for the analog image core (VDD)
Power supply for the reset line drivers (VDDR)
4 analog outputs
M1
VDD_ ARRAY
------------- SKY --------------
3024 x 4536 active pixels
3048 x 4560 total pixels
Top of camera
M2
SELECT
M3
SHS
3024 x 24 dummy pixels
Column
pixel 0,0
PC
SHR
FPN and PRNU
FPN correction is done on-chip using the double sampling
technique. The pixel is read out and this voltage value is sampled
on the capacitor SHS. After readout, the pixel is reset again and
this value is sampled by SHR. Both sample and reset values of
each pixel are subtracted in the column amplifiers to subtract
FPN. Raw images taken by the sensor typically feature a residual
(local) FPN of 0.11% RMS of the saturation voltage.
The photo response nonuniformity (PRNU), caused by mismatch
of photodiode node capacitances, is not corrected on-chip.
Measurements indicate that the typical PRNU is less than 1%
RMS of the signal level.
Output Stage
Unity gain buffers are implemented as output amplifiers. These
amplifiers can be directly DC-coupled to the analog-digital
converter or coupled to an external programmable gain amplifier
(PGA).
The dark reference offset of the output signal is adjustable
between 1.7 V and 3 V. The amplifier output signal is negative
going with increasing light levels, with a maximum amplitude of
1.2 V (at 4 V reset voltage, in hard reset mode). The output signal
range of the output amplifiers is between 0.5 V and 3 V.
Notes on analog video signal and output amplifier specifications:
Video polarity: the video signal is negative going with increasing
light level.
Signal offset: the analog offset of the video signal can be set
by an external DC bias (pin 12 DARKREF). The settable range
is between 1.7 V and 3 V, with 2.65 V being the nominal
expected set point. Hence, the output range (including 1.2 V
video signal) is between 3 V and 0.5 V.
Power control: the output amplifiers can be switched between
an ‘operating’ mode and a ‘standby’ mode via the serial port of
the imager (see
Coupling: the IBIS4-14000 can be DC- or AC-coupled to the
AD converter.
SPI Register
on page 13 for the configuration).
CYII4SM014KAA
Page 6 of 25

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