CYII4SM014KAA-GECU Cypress Semiconductor Corp, CYII4SM014KAA-GECU Datasheet - Page 11

• Manufacturer Part Number: CYII4SM014KAA-GECU
• Description: IC IMAGE SENSOR 14MP CMOS 49-PGA
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYII4SM014KAA-GECU

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

In
used for the electronic shutter. The CLK_YR is driven identically
as CLK_YL. The SYNC_YR pulse leads the SYNC_YL pulse by
a given number of rows. Relative to the row timing, both SYNC
pulses are given at the same time position.
SYNC_YR and SYNC_YL are only pulsed once each frame,
SYNC_YL is pulsed when the first row is read out and SYNC_YR
is pulsed for the electronic shutter at the appropriate moment.
This timing assumes that the registers that control the subsam-
pling modes have been loaded in advance (through the SPI
interface), before the pulse on SYNC_YL or SYNC_YR.
The second reset pulse and the pulses on SYL and SYR (all
pulses drawn in red) are only applied when the rolling electronic
shutter is used. For full frame integration, these pulses are
skipped.
The SYNC_Y pulse is also used to initialize the switchboard
(output multiplexer). This is also done by a synchronous reset on
the rising edge of CLK_Y. Normally the switchboard is controlled
by the shift register used for readout (this is the YL shift register).
This means that pin SYNC_Y can be connected to SYNC_YL,
and pin CLK_Y can be connected to CLK_YL.
The additional RESET BLACK pulse (indicated in dashed lines
in
black. This is useful to generate a dark reference signal.
Timing Pulse Pattern for Readout of a Pixel
Figure 8
register, read out the image row, and analog-digital conversion.
There are 3 tasks:
Document #: 38-05709 Rev. *F
Figure 7
Figure 7
shows the timing diagram to preset (sync) the X shift
on page 10) can be given to make one or more lines
on page 10 timing diagram, the YR shift register is
SYNC_X
CLK_X
Analog
Output
CLK_ADC
(example)
Ts
Figure 8. Row Readout Timing Sequence
X
Ts
■
■
■
The SYNC pulses perform a synchronous reset of the shift
registers to the first row/column on a rising edge on CLK. This is
identical for all shift registers (YR, YL and X).
Note The SYNC_X signal has a setup time Ts of 150 ns. For the
YR and YS shift registers, the setup time is 200 ns. CLK_X must
be stable at least during this setup time.
If a partial row readout is performed, 2 CLK_X pulses (with
SYNC_X = LOW) are required to fully deselect the column where
the X pointer is stopped. A single CLK_X leaves the column
partially selected which then has a different response when read
out in the next row.
When full row readout is performed, the last column is fully
deselected by a single CLK_X pulse (with SYNC_X = LOW). The
X-register is reset by a single CLK_X pulse (with SYNC_X =
LOW). In case of partial row readout, give the SYNC_X pulse
before the sample pulses (SHR and SHS) of the process to avoid
a different response of the last column of the previous window.
For the X shift register the analog signal is delayed by 2 clock
periods before it becomes available at the output (due to internal
processing of the signal in the columns and output amplifier).
Figure 8
samples on the rising edge.
Preset the X shift register: Apply a low level to SYNC_X during
a rising edge on CLK_X at the start of a new row
Readout of the image row: Pulse CLK_X
Analog-digital conversion: Clock the ADC
pixel 1
gives an example of an ADC clock for an ADC that
pixel 2
pixel 3
CYII4SM014KAA
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