MT9V125IA7XTC Aptina LLC, MT9V125IA7XTC Datasheet - Page 3

• Manufacturer Part Number: MT9V125IA7XTC
• Description: SENSOR IMAGE VGA COLOR 52IBGA
• Manufacturer: Aptina LLC
• Series: DigitalClarity®, Micron®r
• Type: CMOS Imagingr

Specifications of MT9V125IA7XTC

• Package / Case: 52-IBGA
• Pixel Size: 5.6µm x 5.6µm
• Active Pixel Array: 640H x 480V
• Frames Per Second: 25 ~ 30
• Voltage - Supply: 2.5 V ~ 3.1 V
• Supply Voltage Range: 2.5V To 3.1V
• Operating Temperature Range: -40°C To +105°C
• Digital Ic Case Style: BGA
• No. Of Pins: 52
• Supply Voltage Max: 3.1V
• Supply Voltage Min: 2.5V
• Ic Function: System-On-A-Chip (SOC) CMOS Digital Image Sensor
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 557-1240 - KIT HEADBOARD FOR MT9V125557-1239 - KIT DEMO FOR MT9V125
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 557-1238

Functional Overview
Internal Architecture
Figure 2:
PDF: 09005aef829db8a0/Source: 09005aef829dbfdb
MT9V125_LDS_2.fm - Rev. A 4/07 EN
DIN_CLK
STANDBY
V
V
D
AA
DD
VAAPIX
EXTCLK
IN
/
/
S
[7:0]
SCLK
D
A
DATA
GND
GND
8
Functional Block Diagram
1/4-inch optical format
True Interlaced Readout
Auto black compensation
Programmable analog gain
Programmable exposure
10-bit ADC
640H x 480V
Image Flow Processor
Auto exposure
Auto white balance
Flicker detect/avoid
Camera Control
Sensor Core
The MT9V125 is a fully-automatic, single-chip camera, requiring only a single power
supply, lens, and clock source for basic operation. Output video is streamed via the cho-
sen output port. The MT9V125 internal registers are configured using a two-wire serial
interface.
The device can be put into a low-power sleep mode by asserting STANDBY and shutting
down the clock. Output signals can be tri-stated. Both tri-stating output signals and
entry into standby mode can be achieved via two-wire serial interface register writes.
The MT9V125 requires an input clock of 27 MHz to support correct NTSC or PAL timing.
Internally, the MT9V125 consists of a sensor core and an image flow processor (IFP). The
IFP is divided in two sections, the color pipe and the camera controller. The sensor core
captures raw images that are then input into the IFP . The color pipe section processes
the incoming stream to create interpolated, color-corrected output, and the camera
controller section controls the sensor core to maintain the desired exposure and color
balance.
The IFP scales the image and an integrated video encoder generates either NTSC or PAL
analog composite output. The MT9V125 supports three different output ports; analog
composite video out, LVDS serial out and CCIR 656 interlaced digital video in parallel 8-
bit format.
Figure 2 shows the major functional blocks of the MT9V125. The built-in NTSC/PAL
encoder and the LVDS formatter allow simultaneous outputs of composite and digital
video signals.
(gains, shutter, etc.)
Sensor control
Control Bus
Image Data
Control Bus
Control Bus
Pixel Data
MT9V125: 1/4-Inch VGA SOC Digital Image Sensor
3
Image Flow Processor
Lens shading correction
Color interpolation
Defect correction
Color correction
Gamma correction
Color conversion + formatting
Horizontal interpolator
Line Buffers
Colorpipe
Micron Technology, Inc., reserves the right to change products or specifications without notice.
SRAM
LVDS Formatter
NTSC and PAL
Encoder
and DAC
and Driver
Functional Overview
©2007 Micron Technology, Inc. All rights reserved.
PIXCLK
FRAME_VALID
LINE_VALID
D
LVDS_OUT_NEG
LVDS_OUT_POS
DAC_OUT_NEG
DAC_OUT_POS
OUT
[7:0]