CY7C1347G-200AXC Cypress Semiconductor Corp, CY7C1347G-200AXC Datasheet - Page 17

• Manufacturer Part Number: CY7C1347G-200AXC
• Description: SRAM (Static RAM)
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1347G-200AXC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Memory Size: 4.5M (128K x 36)
• Speed: 200MHz
• Interface: Parallel
• Voltage - Supply: 3.15 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-LQFP
• Density: 4.5Mb
• Access Time (max): 2.8ns
• Sync/async: Synchronous
• Architecture: SDR
• Clock Freq (max): 200MHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 17b
• Package Type: TQFP
• Operating Temp Range: 0C to 70C
• Number Of Ports: 4
• Supply Current: 265mA
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Word Size: 36b
• Number Of Words: 128K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 428-2115; CY7C1347G-200AXC

Switching Waveforms
Notes
Document #: 38-05516 Rev. *I
20. In this diagram, when CE is LOW, CE
21. The data bus (Q) remains in High Z following a write cycle, unless a new read access is initiated by ADSP or ADSC.
22. GW is HIGH.
Data Out (Q)
Data In (D)
ADDRESS
BW[A:D]
ADSP
ADSC
BWE,
ADV
CLK
OE
CE
A1
High-Z
High-Z
t ADS
t CES
t AS
A2
t ADH
t CEH
t CH
t AH
Back-to-Back READs
t CYC
t CLZ
Q(A1)
t CL
(continued)
1
t CO
is LOW, CE
Q(A2)
t OEHZ
Figure 7. Read/Write Cycle Timing
2
is HIGH, and CE
t WES
t DS
D(A3)
Single WRITE
A3
t DH
t WEH
3
DON’T CARE
is LOW. When CE is HIGH, CE
A4
t OELZ
UNDEFINED
Q(A4)
[20, 21, 22]
1
BURST READ
is HIGH, CE
Q(A4+1)
Q(A4+2)
2
is LOW, or CE
Q(A4+3)
3
is HIGH.
CY7C1347G
D(A5)
A5
Back-to-Back
WRITEs
Page 17 of 24
D(A6)
A6
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