AD5426YRM Analog Devices Inc, AD5426YRM Datasheet - Page 7

• Manufacturer Part Number: AD5426YRM
• Description: 8-IOUT DAC WITH SERIAL ITF I.C.
• Manufacturer: Analog Devices Inc

Specifications of AD5426YRM

• Rohs Compliant: NO
• Rohs Status: RoHS non-compliant
• Design Resources: Unipolar, Precision DC Digital-to-Analog Conversion Using AD5426/32/43 8-Bit to12-Bit DACs (CN0034) Precision, Bipolar Configuration for the AD5426/32/43 8-Bit to12-Bit DACs (CN0036) AC Signal Processing Using AD5426/32/43 Current Output DACs (CN0037) Programmable Gain Element Using AD5426/32/43 Current Output DACs (CN0038)
• Number Of Bits: 8
• Data Interface: Serial
• Number Of Converters: 1
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 10-MSOP, Micro10™, 10-uMAX, 10-uSOP
• Power Dissipation (max): 25µW
• Settling Time: 50ns

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 4. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
Mnemonic
I
I
GND
SCLK
SDIN
SYNC
SDO
V
V
R
OUT
OUT
DD
REF
FB
1
2
Description
DAC Current Output.
DAC Analog Ground. This pin should normally be tied to the analog ground of the system.
Digital Ground Pin.
Serial Clock Input. By default, data is clocked into the input shift register on the falling edge of the serial clock
input. Alternatively, by means of the serial control bits, the device may be configured such that data is clocked
into the shift register on the rising edge of SCLK. The device can accommodate clock rates up to 50 MHz.
Serial Data Input. Data is clocked into the 16-bit input register on the active edge of the serial clock input. By
default, on power-up, data is clocked into the shift register on the falling edge of SCLK. The control bits allow the
user to change the active edge to rising edge.
Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low, it
powers on the SCLK and DIN buffers, and the input shift register is enabled. Data is loaded to the mode, the serial
interface counts clocks, and data is latched to the shift register on the 16th active clock edge.
Serial Data Output. This allows a number of parts to be daisy-chained. By default, data is clocked into the shift
register on the falling edge and out via SDO on the rising edge of SCLK. Data is always clocked out on the
alternate edge to loading data to the shift register. Writing the readback control word to the shift register makes
the DAC register contents available for readback on the SDO pin, clocked out on the opposite edges to the active
clock edge.
Positive Power Supply Input. These parts can be operated from a supply of 3 V to 5.5 V.
DAC Reference Voltage Input.
DAC Feedback Resistor Pin. Establish voltage output for the DAC by connecting to external amplifier output.
SCLK
I
I
OUT
OUT
SDIN
GND
1
2
Figure 5. Pin Configuration
1
2
3
4
5
Rev. C | Page 7 of 28
(Not to Scale)
AD5426/
AD5432/
AD5443
TOP VIEW
10
9
8
7
6
R
V
V
SDO
SYNC
REF
DD
FB
AD5426/AD5432/AD5443