KSZ8041RNL-EVAL Micrel Inc, KSZ8041RNL-EVAL Datasheet - Page 12

• Manufacturer Part Number: KSZ8041RNL-EVAL
• Description: BOARD EVALUATION FOR KSZ8041RNL
• Manufacturer: Micrel Inc

Specifications of KSZ8041RNL-EVAL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 576-3863

Pin Differences Between KSZ8041NL and KSZ8051MNL
This section provides information about pin changes that have occurred with the KSZ8051MNL.
Table 14 identifies the pin differences between the KSZ8041NL and the KSZ8051MNL. Changes are shown underlined.
Pins that are not listed are the same for both products.
Micrel, Inc.
Pin
Number
2
11
17
19
21
22
30
31
December 2010
Pin Name
VDDPLL_1.8
MDIO
VDDIO_3.3
RXC
INTRP
TXC
LED0 /
NWAYEN
LED1 /
SPEED
P
Opu
Ipu/O
Ipu/O
Type
I/O
P
O
O
KSZ8041NL
Table 14. Pin Differences (KSZ8041NL and KSZ8051MNL)
Pin Function
1.8V analog VDD
Management Interface
(MII) Data I/O
This pin requires an
external 4.7KΩ pull-up
resistor.
3.3V digital VDD
MII Mode: Receive Clock
Output
Interrupt Output:
Interrupt Output
Register 1Bh is the
Interrupt Control/Status
Register for programming
the interrupt conditions and
reading the interrupt status.
Register 1Fh bit 9 sets the
interrupt output to active
low (default) or active high.
MII Mode: Transmit Clock
Output
The LED0 pin is
programmable via register
1Eh bits [15:14]
The LED1 pin is
programmable via register
1Eh bits [15:14]
Programmable
12
Pin Name
VDD_1.2
MDIO
VDDIO
RXC /
B-CAST_OFF
INTRP /
NAND_Tree#
TXC
LED0 /
NWAYEN
LED1 /
SPEED
Type
P
I/O
P
Ipd/O
Ipu/Opu
I/O
Ipu/O
Ipu/O
KSZ8051MNL
1.2V core VDD
supplied by KSZ8051MNL)
Decouple with 2.2μF and
0.1μF capacitors-to-ground.
Management Interface (MII)
Data I/O
This pin has a weak pull-up, is
open drain like, and requires
an external 1.0KΩ pull-up
resistor.
MII Mode: MII Receive Clock
Output
Config Mode: The pull-up/pull-
down value is latched as B-
CAST_OFF at the de-assertion
of reset.
assertion of reset. See
“Strapping Options” section for
details.
Interrupt Output:
Interrupt Output
This pin has a weak pull-up, is
open drain like, and requires
an external 1.0KΩ pull-up
resistor.
Config Mode: The pull-up/pull-
down value is latched as
NAND Tree# at the de-
assertion of reset.
See “Strapping Options”
section for details.
MII Mode: MII Transmit Clock
Output
MII Back-to-Back Mode:
MII Transmit Clock Input
The LED0 pin is
programmable via register 1Fh
bits [5:4]
The LED1 pin is
programmable via register 1Fh
bits [5:4]
Pin Function
3.3V, 2.5V or 1.8V digital VDD
Application Note 143
Programmable
de-assertion of reset.
M9999-120610-A
(power
de-