KSZ8041RNL-EVAL Micrel Inc, KSZ8041RNL-EVAL Datasheet
KSZ8041RNL-EVAL
Specifications of KSZ8041RNL-EVAL
Related parts for KSZ8041RNL-EVAL
KSZ8041RNL-EVAL Summary of contents
Page 1
... Data Sheet Rev. 1.4 performance and is an ideal choice of physical layer transceiver for 10Base-T/100Base-TX applications. The KSZ8041RNL is an enhanced RMII version of the KSZ8041NL that does not require a 50MHz system clock. It uses a 25MHz crystal for its input reference clock and outputs a 50MHz RMII reference clock to the MAC. ...
Page 2
... RMII interface support with external 50MHz system clock (KSZ8041NL only) • RMII interface support with 25MHz crystal/clock input and 50MHz reference clock output to MAC (KSZ8041RNL only) • MIIM (MDC/MDIO) management bus to 6.25MHz for rapid PHY register configuration • Interrupt pin option • ...
Page 3
... Changed strapping pin definition for CONFIG[2:0] = 100 from “PCS Loopback” to “MII 100Mbps Preamble Restore.” Corrected MII timing for t Added KSZ8041RNL device and updated entire data sheet accordingly. 1.4 01/19/10 Removed part number (KSZ8041NL EAM) from Ordering Information. ...
Page 4
... Pin Description – KSZ8041NL (continued) ....................................................................................................................... 12 Pin Description – KSZ8041NL (continued) ....................................................................................................................... 13 Strapping Options – KSZ8041NL....................................................................................................................................... 14 Pin Configuration – KSZ8041RNL ..................................................................................................................................... 15 Pin Description – KSZ8041RNL ......................................................................................................................................... 16 Pin Description – KSZ8041RNL (continued) .................................................................................................................... 17 Pin Description – KSZ8041RNL (continued) .................................................................................................................... 18 Strapping Options – KSZ8041RNL .................................................................................................................................... 19 Functional Description ....................................................................................................................................................... 20 100Base-TX Transmit....................................................................................................................................................... 20 100Base-TX Receive........................................................................................................................................................ 20 PLL Clock Synthesizer...................................................................................................................................................... 20 Scrambler/De-scrambler (100Base-TX only) ...
Page 5
Micrel, Inc. Reduced MII (RMII) Data Interface................................................................................................................................... 25 RMII Signal Definition ....................................................................................................................................................... 26 Reference Clock (REF_CLK) ....................................................................................................................................... 26 Transmit Enable (TX_EN) ............................................................................................................................................ 26 Transmit Data [1:0] (TXD[1:0]) ..................................................................................................................................... 26 Carrier Sense/Receive Data Valid (CRS_DV).............................................................................................................. 27 Receive Data [1:0] (RXD[1:0]) ...................................................................................................................................... ...
Page 6
Micrel, Inc. Reset Circuit ........................................................................................................................................................................ 51 Reference Circuits for LED Strapping Pins...................................................................................................................... 52 Selection of Isolation Transformer.................................................................................................................................... S election of Reference Crystal .......................................................................................................................................... ackage Information........................................................................................................................................................... September 2010 6 KSZ8041NL/RNL ...
Page 7
... Micrel, Inc. List of Figures Figure 1. Auto-Negotiation Flow Chart................................................................................................................................. 22 Figure 2. KSZ8041NL RMII Interface................................................................................................................................... 27 Figure 3. KSZ8041RNL RMII Interface ................................................................................................................................ 28 Figure 4. Typical Straight Cable Connection ....................................................................................................................... 29 Figure 5. Typical Crossover Cable Connection ................................................................................................................... 29 Figure 6. 25MHz Crystal / Oscillator Reference Clock ........................................................................................................ 30 Figure 7. 50MHz Oscillator Reference Clock for KSZ8041NL RMII Mode .......................................................................... 30 Figure 8 ...
Page 8
... List of Tables Table 1. MII Management Frame Format ............................................................................................................................ 23 Table 2. MII Signal Definition ............................................................................................................................................... 24 Table 3. RMII Signal Description – KSZ8041NL.................................................................................................................. 26 Table 4. RMII Signal Description – KSZ8041RNL ............................................................................................................... 26 Table 5. MDI/MDI-X Pin Definition ....................................................................................................................................... 28 Table 6. KSZ8041NL/RNL Power Pin Description............................................................................................................... 31 Table 7. MII SQE Timing (10Base-T) Parameters ............................................................................................................... 42 Table 8. MII Transmit Timing (10Base-T) Parameters ........................................................................................................ 43 Table 9 ...
Page 9
Micrel, Inc. Pin Configuration – KSZ8041NL September 2010 ® 32-Pin (5mm x 5mm) MLF 9 KSZ8041NL/RNL M9999-090910-1.4 ...
Page 10
Micrel, Inc. Pin Description – KSZ8041NL Pin Number Pin Name Type 1 GND Gnd 2 VDDPLL_1.8 3 VDDA_3.3 4 RX- I/O 5 RX+ I/O 6 TX- I/O 7 TX+ I REFCLK 10 REXT I/O 11 ...
Page 11
Micrel, Inc. Pin Description – KSZ8041NL (Continued) Pin Number Pin Name Type 20 RXER / Ipd/O RX_ER / ISO 21 INTRP Opu 22 TXC 23 TXEN / TX_EN 24 TXD0 / TXD[0] 25 TXD1 / TXD[1] 26 TXD2 27 TXD3 ...
Page 12
Micrel, Inc. Pin Description – KSZ8041NL (Continued) Pin Number Pin Name Type 30 LED0 / Ipu/O NWAYEN September 2010 (1) Pin Function LED Output: Programmable LED0 Output / Config Mode: Latched as Auto-Negotiation Enable (register 0h, bit 12) during power-up ...
Page 13
Micrel, Inc. Pin Description – KSZ8041NL (Continued) Pin Number Pin Name Type 31 LED1 / Ipu/O SPEED 32 RST# I PADDLE GND Gnd Notes Power supply. Gnd = Ground Input Output. I/O = ...
Page 14
Micrel, Inc. Strapping Options – KSZ8041NL Pin Number Pin Name Type 15 PHYAD2 Ipd/O 14 PHYAD1 Ipd/O PHYAD0 Ipu CONFIG2 Ipd/O 29 CONFIG1 Ipd/O 28 CONFIG0 Ipd/O 20 ISO Ipd/O 31 SPEED Ipu/O 16 DUPLEX Ipu/O 30 NWAYEN ...
Page 15
... Micrel, Inc. Pin Configuration – KSZ8041RNL September 2010 ® 32-Pin (5mm x 5mm) MLF 15 KSZ8041NL/RNL M9999-090910-1.4 ...
Page 16
... Crystal / Oscillator / External Clock Input 25MHz +/-50ppm Set physical transmit output current Connect a 6.49KΩ resistor in parallel with a 100pF capacitor to ground on this pin. See KSZ8041RNL reference schematics. Management Interface (MII) Data I/O This pin requires an external 4.7KΩ pull-up resistor. I Management Interface (MII) Clock Input This pin is synchronous to the MDIO data interface ...
Page 17
... Micrel, Inc. Pin Description – KSZ8041RNL (Continued) Pin Number Pin Name Type 24 TXD0 25 TXD1 CONFIG0 Ipd/O 29 CONFIG1 Ipd/O 30 LED0 / Ipu/O NWAYEN September 2010 (1) Pin Function (3) I RMII Transmit Data Input[0] (3) I RMII Transmit Data Input[ connect I No connect The pull-up/pull-down value is latched as CONFIG0 during power-up / reset. ...
Page 18
... Micrel, Inc. Pin Description – KSZ8041RNL (Continued) Pin Number Pin Name Type 31 LED1 / Ipu/O SPEED 32 RST# PADDLE GND Gnd Notes Power supply. Gnd = Ground Input Output. I/O = Bi-directional. Opu = Output with internal pull-up (40K +/-30%). Ipu/O = Input with internal pull-up (40K +/-30%) during power-up/reset; output pin otherwise. ...
Page 19
... Micrel, Inc. Strapping Options – KSZ8041RNL Pin Number Pin Name Type 15 PHYAD2 14 PHYAD1 13 PHYAD0 18 CONFIG2 29 CONFIG1 28 CONFIG0 20 ISO 31 SPEED 16 DUPLEX 30 NWAYEN Note: 1. Ipu/O = Input with internal pull-up (40K +/-30%) during power-up/reset; output pin otherwise. Ipd/O = Input with internal pull-down (40K +/-30%) during power-up/reset; output pin otherwise. ...
Page 20
... The KSZ8041RNL is an enhanced RMII version of the KSZ8041NL that does not require a 50MHz system clock. It uses a 25MHz crystal for its input reference clock and outputs a 50MHz RMII reference clock to the MAC. ...
Page 21
Micrel, Inc. 10Base-T Receive On the receive side, input buffer and level detecting squelch circuits are employed. A differential input receiver circuit and a PLL performs the decoding function. The Manchester-encoded data stream is separated into clock signal and NRZ ...
Page 22
Micrel, Inc. Start Auto Negotiation Force Link Setting Yes Bypass Auto Negotiation and Set Link Mode September 2010 N Parallel Operation o Attempt Auto Listen for 100BASE-TX Negotiation Idles Join Flow Link Mode Set ? Yes Link Mode Set Figure ...
Page 23
Micrel, Inc. MII Management (MIIM) Interface The KSZ8041NL/RNL supports the IEEE 802.3 MII Management Interface, also known as the Management Data Input / Output (MDIO) Interface. This interface allows upper-layer devices to monitor and control the state of the KSZ8041NL/RNL. ...
Page 24
Micrel, Inc. MII Signal Definition (KSZ8041NL only) The Table 2 describes the MII signals. Refer to Clause 22 of the IEEE 802.3 Specification for detailed information. Direction MII (with respect to PHY, Signal Name KSZ8041NL signal) TXC Output TXEN Input ...
Page 25
... A 50MHz reference clock connected to REFCLK (pin 9). • CONFIG[2:0] (pins 18, 29, 28) set to ‘001’. The KSZ8041RNL is configured in RMII mode and outputs the 50MHz RMII reference clock to the MAC on REF_CLK (pin 19) after it is power-up or reset with the following: • A 25MHz crystal connected to XI (pin 9) and XO (pin 8 25MHz reference clock connected to XI (pin 9). ...
Page 26
... Micrel, Inc. RMII Signal Definition The Tables 3 and 4 describe the RMII signals for KSZ8041NL and KSZ8041RNL. Refer to RMII Specification for detailed information. Direction RMII (with respect to PHY, Signal Name KSZ8041NL signal) REF_CLK Input TX_EN Input TXD[1:0] Input CRS_DV Output RXD[1:0] Output ...
Page 27
Micrel, Inc. Carrier Sense/Receive Data Valid (CRS_DV) CRS_DV is asserted by the PHY when the receive medium is non-idle asserted asynchronously on detection of carrier. This is when squelch is passed in 10Mbps mode, and when 2 non-contiguous ...
Page 28
... Micrel, Inc. The KSZ8041RNL RMII pin connections to the MAC are shown in Figure 3. HP Auto MDI/MDI-X HP Auto MDI/MDI-X configuration eliminates the confusion of whether to use a straight cable or a crossover cable between the KSZ8041NL/RNL and its link partner. This feature allows the KSZ8041NL/RNL to use either type of cable to connect with a link partner that is in either MDI or MDI-X mode ...
Page 29
Micrel, Inc. Straight Cable A straight cable connects a MDI device to a MDI-X device MDI-X device to a MDI device. The Figure 4 depicts a typical straight cable connection between a NIC card (MDI) and a switch, ...
Page 30
Micrel, Inc. Power Management The KSZ8041NL/RNL offers the following power management modes: Power Saving Mode This mode is used to reduce power consumption when the cable is unplugged effect when auto-negotiation mode is enabled, cable is disconnected, ...
Page 31
Micrel, Inc. Reference Circuit for Power and Ground Connections The KSZ8041NL/RNL is a single 3.3V supply device with a built-in 1.8V low noise regulator. The power and ground connections are shown in Figure 8 and Table 6. Ferrite Bead 22uF ...
Page 32
Micrel, Inc. Register Map Register Number (Hex) Description 0h Basic Control 1h Basic Status 2h PHY Identifier 1 3h PHY Identifier 2 4h Auto-Negotiation Advertisement 5h Auto-Negotiation Link Partner Ability 6h Auto-Negotiation Expansion 7h Auto-Negotiation Next Page 8h Link Partner ...
Page 33
Micrel, Inc. Register Description (Continued) Address Name Description Register 0h – Basic Control 0.9 Restart Auto Restart auto-negotiation process Negotiation 0 = Normal operation. This bit is self-cleared after a ‘1’ is written to it. 0.8 Duplex Mode ...
Page 34
Micrel, Inc. Register Description (Continued) Address Name Description Register 2h – PHY Identifier 1 2.15:0 PHY ID Assigned to the 3rd through 18th bits of the Number Organizationally Unique Identifier (OUI). Kendin Communication’s OUI is 0010A1 (hex) Register 3h – ...
Page 35
Micrel, Inc. Register Description (Continued) Address Name Description Register 5h – Auto-Negotiation Link Partner Ability 5.15 Next Page 1 = Next page capable next page capability 5.14 Acknowledge 1 = Link code word received from partner 0 ...
Page 36
Micrel, Inc. Register Description (Continued) Address Name Description Register 7h – Auto-Negotiation Next Page 7.15 Next Page 1 = Additional next page(s) will follow 0 = Last page 7.14 Reserved 7.13 Message Page 1 = Message page 0 = Unformatted ...
Page 37
Micrel, Inc. Register Description (Continued) Address Name Description Register 1Bh – Interrupt Control/Status 1b.15 Jabber 1 = Enable Jabber Interrupt Interrupt 0 = Disable Jabber Interrupt Enable Receive Error 1b. Enable Receive Error Interrupt Interrupt 0 = Disable ...
Page 38
Micrel, Inc. Register Description (Continued) Address Name Description Register 1Eh – PHY Control 1 1e:15:14 LED mode [00] = [01] = [10], [11] = Reserved 1e.13 Polarity 0 = Polarity is not reversed 1 = Polarity is reversed 1e.12 Reserved ...
Page 39
Micrel, Inc. Register Description (Continued) Address Name Description 1f.10 Power Saving 1 = Enable power saving 0 = Disable power saving If power saving mode is enabled and the cable is disconnected, the RXC clock output (in MII mode) is ...
Page 40
Micrel, Inc. Absolute Maximum Ratings Supply Voltage (V ) ............................................... -0.5V to +2.4V DDPLL_1 ................................... -0.5V to +4.0V DDIO_3.3, DDA_3.3 Input Voltage (all inputs) ............................... -0.5V to +4.0V Output Voltage (all outputs) .......................... -0.5V to +4.0V Lead ...
Page 41
Micrel, Inc. Electrical Characteristics Symbol Parameter 10Base-T Transmit (measured differentially after 1:1 transformer) V Peak Differential Output Voltage P Jitter Added Rise/Fall Time r f 10Base-T Receive V Squelch Threshold SQ Notes: 1. Exceeding the absolute maximum ...
Page 42
Micrel, Inc. Timing Diagrams MII SQE Timing (10Base-T) Timing Parameter SQE t SQEP September 2010 Figure 9. MII SQE Timing (10Base-T) Description TXC period TXC pulse width low TXC pulse width high COL ...
Page 43
Micrel, Inc. MII Transmit Timing (10Base-T) Timing Parameter SU1 t SU2 t HD1 t HD2 t CRS1 t CRS2 September 2010 Figure 10. MII Transmit Timing (10Base-T) Description TXC period TXC pulse width ...
Page 44
Micrel, Inc. MII Receive Timing (10Base-T) Timing Parameter RLAT September 2010 Figure 11. MII Receive Timing (10Base-T) Description RXC period RXC pulse width low RXC pulse width high (RXD[3:0], RXER, RXDV) ...
Page 45
Micrel, Inc. MII Transmit Timing (100Base-TX) Timing Parameter SU1 t SU2 t HD1 t HD2 t CRS1 t CRS2 September 2010 Figure 12. MII Transmit Timing (100Base-TX) Description TXC period TXC pulse width ...
Page 46
Micrel, Inc. MII Receive Timing (100Base-TX) Timing Parameter RLAT September 2010 Figure 13. MII Receive Timing (100Base-TX) Description RXC period RXC pulse width low RXC pulse width high (RXD[3:0], RXER, RXDV) ...
Page 47
... Figure 15. RMII Timing – Data Input to RMII Description Min Clock cycle Setup time 4 Hold time 2 Output delay 3 Table 12. RMII Timing Parameters – KSZ8041NL Description Min Clock cycle Setup time 4 Hold time 1 Output delay 9 Table 13. RMII Timing Parameters – KSZ8041RNL 47 KSZ8041NL/RNL Typ Max Unit Typ Max Unit ...
Page 48
Micrel, Inc. Auto-Negotiation Timing Timing Parameter t BTB t FLPW CTD t CTC Table 14. Auto-Negotiation Fast Link Pulse (FLP) Timing Parameters September 2010 Figure 16. Auto-Negotiation Fast Link Pulse (FLP) Timing Description FLP Burst to FLP ...
Page 49
Micrel, Inc. MDC/MDIO Timing Timing Parameter Description t MDC period P t MDIO (PHY input) setup to rising edge of MDC 1MD1 t MDIO (PHY input) hold from rising edge of MDC MD2 t MDIO (PHY output) delay from rising ...
Page 50
Micrel, Inc. Reset Timing The KSZ8041NL/RNL reset timing requirement is summarized in the following figure and table. Parameter After the de-assertion of reset recommended to wait a minimum of 100 ...
Page 51
Micrel, Inc. Reset Circuit The reset circuit in Figure 19 is recommended for powering up the KSZ8041NL/RNL if reset is triggered by the power supply. The reset circuit in Figure 20 is recommended for applications where reset is driven by ...
Page 52
Micrel, Inc. Reference Circuits for LED Strapping Pins The Figure 21 shows the reference circuits for pull-up, float and pull-down on the LED1 and LED0 strapping pins. September 2010 Pull-up KSZ8041NL/RNL LED pin Float KSZ8041NL/RNL LED pin Pull-down KSZ8041NL/RNL LED ...
Page 53
Micrel, Inc. Selection of Isolation Transformer A 1:1 isolation transformer is required at the line interface. An isolation transformer with integrated common-mode chokes is recommended for exceeding FCC requirements. The Table 17 gives recommended transformer characteristics. Parameter Turns ratio Open-circuit ...
Page 54
Micrel, Inc. Package Information MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, ...