CMD-12DP512 AXIOM, CMD-12DP512 Datasheet - Page 5

• Manufacturer Part Number: CMD-12DP512
• Description: Single Board Computer
• Manufacturer: AXIOM

Specifications of CMD-12DP512

• Silicon Manufacturer: Freescale
• Core Architecture: HCS12
• Core Sub-architecture: S12D
• Features: Onboard Back Ground Debug, Breadboard And Prototype Area
• Kit Contents: Board
• Silicon Family Name: S12D
• Silicon Core Number: MC9S12DP512

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Default Options Summary
AxIDE4 OPERATION
The AxIDE4 software will apply the CMD-12DP512 USB port (BDM) for connection to the
development board. Refer to the AxIDE4 User Manual for establishing a connection with the
CMD-12DP512 board. The STATUS indicator near the USB port on the board provides an
indication of connection with the software.
Connection to the development board is not required to edit and compile application software
with AxIDE4. Connection is required to load or “Debug” the application on the board. User
should note that the software Memory target type, register settings, and CMD-12DP512 board
options must be set and reviewed together for proper operation when the application is loaded.
Refer to the Target Memory Option Table to review these settings.
The CMD-12DP512 board may be configured to emulate HCS12 device internal flash memory
in the external board Ram memory space. This feature allows the BDM (Background Debug
Module) to load and control the execution of code being developed without the necessity of the
internal flash memory being programmed.
Operation Notes for BDM use:
1)
2)
3)
BDM_EN
CAN_EN
COM_SEL
JP1
JP2
PWR_SEL
LCD_EN
NO_AUTO
MODE
ECS
MEM_EN
For BDM use the default HCS12 Mode is Single-Chip and the board MODE option
installed. The BDM initialization of the HCS12 will set the correct operating Mode
(Expanded Wide for external memory access) as required to properly load the board
memory. The user application code should also perform the Expanded Wide
configuration for external memory access even if the MODE is optioned for Expanded.
See the MODE option for additional details.
While using the BDM, the user has full control over the memory map and hardware
resources of the HCS12. No resources are required to be reserved and the user may
apply the physical HCS12 interrupt vector table located at 0xFF80 - 0xFFFF. The
internal HCS12 flash may be disabled for emulation of the flash memory space in the
board external RAM memory. Refer to the HC12 MISC register for internal flash
memory mapping options.
The BDM provides optional power and serial port connections, review limitations for
these settings in the COM_SEL and PWR_SEL option sections.
R E V
IN (both)
IN
USB
IN
OUT
USB
IN
OUT
IN
OUT
IN
B .
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