STM32F103ZGH6 STMicroelectronics, STM32F103ZGH6 Datasheet - Page 97

• Manufacturer Part Number: STM32F103ZGH6
• Description: MCU 32BIT 1MB FLASH 144LQFP
• Manufacturer: STMicroelectronics
• Series: STM32r

Specifications of STM32F103ZGH6

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 72MHz
• Connectivity: CAN, I²C, IrDA, LIN, MMC, SPI, UART/USART, USB
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 112
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 96K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 21x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Processor Series: STM32F101xG
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 80 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 36 MHz
• Number Of Programmable I/os: 112
• Number Of Timers: 15
• Operating Supply Voltage: 2 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Operating Temperature Range: - 40 C to + 105 C
• Processor To Be Evaluated: STM32F103ZG
• Supply Current (max): 28 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 497-11115

STM32F103xF, STM32F103xG
Table 54.
1. Based on design simulation and/or characterization results, not tested in production.
2. Depends on f
DuCy(SCK)
f
1/t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
CK
r(CK)
f(CK)
v(WS)
h(WS)
su(WS)
h(WS)
w(CKH)
w(CKL)
su(SD_MR)
su(SD_SR)
h(SD_MR)
h(SD_SR)
v(SD_ST)
h(SD_ST)
v(SD_MT)
h(SD_MT)
c(CK)
Symbol
(1)
(1)
(1)
(1)
(1)
(1)
(1)(2)
(1)(2)
(1)
(1)(2)
(1)(2)
(1)
(1)
(1)
I
2
PCLK
S characteristics
I2S slave input clock duty
cycle
I
I
WS valid time
WS hold time
WS setup time
WS hold time
CK high and low time
Data input setup time
Data input setup time
Data input hold time
Data output valid time
Data output hold time
Data output valid time
Data output hold time
2
2
S clock frequency
S clock rise and fall time
. For example, if f
Parameter
PCLK
=8 MHz, then T
Slave mode
Master mode (data: 16 bits,
Audio frequency = 48 kHz)
Slave mode
Capacitive load C
Master mode
Master mode
Slave mode
Slave mode
Master f
frequency = 48 kHz
Master receiver
Slave receiver
Master receiver
Slave receiver
Slave transmitter (after enable
edge)
Slave transmitter (after enable
edge)
Master transmitter (after enable
edge)
Master transmitter (after enable
edge)
Doc ID 16554 Rev 2
PCLK
PCLK
Conditions
= 1/f
= 16 MHz, audio
PLCLK
L
= 50 pF
=125 ns.
I2S2
I2S3
I2S2
I2S3
1.522
312.5
Min
345
6.5
1.5
0.5
30
11
0
3
2
0
4
0
2
0
0
Electrical characteristics
1.525
Max
70
6.5
18
8
3
MHz
Unit
ns
%
97/120