S29AL008D70TFI020 Spansion Inc., S29AL008D70TFI020 Datasheet - Page 13

• Manufacturer Part Number: S29AL008D70TFI020
• Description: Flash Memory IC
• Manufacturer: Spansion Inc.

Specifications of S29AL008D70TFI020

• Memory Size: 8Mbit
• Memory Configuration: 1M X 8 / 512K X 16
• Ic Interface Type: Parallel
• Access Time: 70ns
• Memory Case Style: TSOP
• No. Of Pins: 48
• Operating Temperature Range: -40°C To +85°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

June 16, 2005 S29AL008D_00A3
Automatic Sleep Mode
RESET#: Hardware Reset Pin
Output Disable Mode
The device enters the CMOS standby mode when the CE# and RESET# pins are
both held at V
V
is in the standby mode, but the standby current is greater. The device requires
standard access time (t
standby modes, before it is ready to read data.
If the device is deselected during erasure or programming, the device draws ac-
tive current until the operation is completed.
In the DC Characteristics table, I
specification.
The automatic sleep mode minimizes Flash device energy consumption. The de-
vice automatically enables this mode when addresses remain stable for t
ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control
signals. Standard address access timings provide new data when addresses are
changed. While in sleep mode, output data is latched and always available to the
system. I
current specification.
The RESET# pin provides a hardware method of resetting the device to reading
array data. When the RESET# pin is driven low for at least a period of t
device immediately terminates any operation in progress, tristates all output
pins, and ignores all read/write commands for the duration of the RESET# pulse.
The device also resets the internal state machine to reading array data. The op-
eration that was interrupted should be reinitiated once the device is ready to
accept another command sequence, to ensure data integrity.
Current is reduced for the duration of the RESET# pulse. When RESET# is held
at V
at V
The RESET# pin may be tied to the system reset circuitry. A system reset would
thus also reset the Flash memory, enabling the system to read the boot-up firm-
ware from the Flash memory.
If RESET# is asserted during a program or erase operation, the RY/BY# pin re-
mains a 0 (busy) until the internal reset operation is complete, which requires a
time of t
BY# to determine whether the reset operation is complete. If RESET# is asserted
when a program or erase operation is not executing (RY/BY# pin is 1), the reset
operation is completed within a time of t
The system can read data t
Refer to
14, on page 39
When the OE# input is at V
are placed in the high impedance state.
IH
.) If CE# and RESET# are held at V
IL
SS
±0.3 V, the device draws CMOS standby current (I
but not within V
READY
CC4
AC Characteristics, on page 38
in the DC Characteristics table represents the automatic sleep mode
CC
(during Embedded Algorithms). The system can thus monitor RY/
for the timing diagram.
± 0.3 V. (Note that this is a more restricted voltage range than
D a t a
SS
CE
±0.3 V, the standby current is greater.
) for read access when the device is in either of these
IH
RH
, output from the device is disabled. The output pins
after the RESET# pin returns to V
S h e e t
CC3
S29AL008D
and I
IH
READY
, but not within V
for RESET# parameters and to
CC4
(not during Embedded Algorithms).
represents the standby current
CC4
CC
). If RESET# is held
± 0.3 V, the device
IH
.
ACC
RP
Figure
, the
+ 30
13