PIC18F2423-I/ML Microchip Technology, PIC18F2423-I/ML Datasheet - Page 11

• Manufacturer Part Number: PIC18F2423-I/ML
• Description: 16KB, Flash, 768bytes-RAM, 25I/O, 8-bit Family,nanoWatt 28 QFN 6x6mm TUBE
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F2423-I/ML

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 10x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT28QFN4 - SOCKET TRANS ICE 28QFN W/CABLEAC164322 - MODULE SOCKET MPLAB PM3 28/44QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

FIGURE 3-2:
3.1.2
When using low-voltage ICSP, the part must be
supplied by the voltage specified in parameter D111 if a
Bulk Erase is to be executed. All other Bulk Erase
details as described above apply.
If it is determined that a program memory erase must
be performed at a supply voltage below the Bulk Erase
limit, refer to the erase methodology described in
Section 3.1.3 “ICSP Row Erase” and Section 3.2.1
“Modifying Code Memory”.
If it is determined that a data EEPROM erase
(selected devices only, see Section 3.3 “Data
EEPROM Programming”) must be performed at a
supply voltage below the Bulk Erase limit, follow the
methodology
EEPROM Programming” and write ‘1’s to the array.
© 2005 Microchip Technology Inc.
PGC
PGD
4-Bit Command
1
0
LOW-VOLTAGE ICSP BULK ERASE
2
0
3
1
described
4
1
P5
BULK ERASE TIMING
1
1
Data Payload
2
1
16-Bit
in
15 16
Section 3.3
0
0
P5A
4-Bit Command
1
0
PIC18F2423/2523/4423/4523
2
0
“Data
3
0
PGD = Input
4
0
P5
1
0
Data Payload
2
0
16-Bit
3.1.3
Regardless of whether high or low-voltage ICSP is
used, it is possible to erase one row (64 bytes of data),
provided the block is not code or write-protected. Rows
are located at static boundaries, beginning at program
memory address 000000h, extending to the internal
program memory limit (see Section 2.3 “Memory
Maps”).
The Row Erase duration is externally timed and is
controlled by PGC. After the WR bit in EECON1 is set,
a NOP is issued, where the 4th PGC is held high for the
duration of the programming time, P9.
After PGC is brought low, the programming sequence
is terminated. PGC must be held low for the time
specified by parameter P10 to allow high-voltage
discharge of the memory array.
The code sequence to Row Erase a PIC18F2423/2523/
4423/4523 device is shown in Table 3-3. The flowchart
shown in Figure 3-3 depicts the logic necessary to
completely
device. The timing diagram that details the Start
Programming command and parameters P9 and P10 is
shown in Figure 3-5.
15 16
Note:
0
0
P5A
4-Bit Command
1
ICSP ROW ERASE
The TBLPTR register can point at any byte
within the row intended for erase.
0
erase
2
0
3
0
4
0
a
PIC18F2423/2523/4423/4523
Erase Time
P11
DS39759A-page 11
P10
Data Payload
16-Bit
1
n
2
n