STA328 STMicroelectronics, STA328 Datasheet
STA328
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STA328 Summary of contents
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... THD ! Four output routing configurations ! Selectable clock input ratio ! 96 kHz internal processing sample rate 28-bit precision ! Video application supports 576 * fs input mode. Package PowerSO-36 PowerSO-36 Rev 4 STA328 PowerSO-36 with slug up ® ternary or binary PWM Packaging Tube Tape and reel www.st.com 1/57 1 ...
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... Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.1 Configuration register A (addr 0x00 6.2 Configuration register B (addr 0x01 6.3 Configuration register C (addr 0x02 6.3.1 6.3.2 6.4 Configuration register D (addr 0x03 6.5 Configuration register E (addr 0x04 2/57 ® DDX power output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 ® DDX variable compensating pulse size . . . . . . . . . . . . . . . . . . . . . . . . 26 STA328 ...
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... STA328 6.6 Configuration register F (addr 0x05 6.7 Volume control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.7.1 6.7.2 6.7.3 6.8 AutoMode registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6.8.1 6.8.2 6.8.3 6.9 Channel configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 6.9.1 6.9.2 6.9.3 6.10 Tone control (addr 0x11 6.11 Dynamics control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 6.11.1 6.11.2 6.11.3 6.11.4 6.11.5 6.11.6 6.11.7 7 User programmable processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 7 ...
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... Coefficient a2 data register bits 15:8 (addr 0x21 Coefficient a2 data register bits 7:0 (addr 0x22 Coefficient b0 data register bits 23:16 (addr 0x23 Coefficient b0 data register bits 15:8 (addr 0x24 Coefficient b0 data register bits 7:0 (addr 0x25 Coefficient write control register (addr 0x26 STA328 ...
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... The IC can also be configured as a single parallel full-bridge capable of high-current operation and 1 x 160 W output. Also provided in the STA328 is a full assortment of digital processing features. This includes up to four programmable 28-bit biquads (EQ) per channel and bass/treble tone control. AutoModes enable a time-to-market advantage by substantially reducing the amount of software development needed for certain functions ...
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... OUT2B De- Bass T reble BQ#4 Emphasis Filter Filter T o Mix If CxT Bass Boost/Cut If DEMP = reble Boost/Cut 2-channel (full-bridge) configuration, register bits OCFG[1: 2.1-channel configuration, register bits OCFG[1: 1-channel mono-parallel configuration, register bits OCFG[1: The setup register is Configuration register F (addr 0x05) on page 31 STA328 ...
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... STA328 1.4 Applications Figure 5. Application circuit for 2.1/2.0 configurable solution Description 7/57 ...
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... Not connected GND2B Negative supply GND2A Negative supply VCC2A Positive supply OUT2A Output half bridge 2A OUT1B Output half bridge 1B VCC1B Positive supply GND1B Negative supply GND1A Negative supply N.C. Not connected STA328 SUB_GND 1 N.C. 2 OUT2B 3 VCC2B 4 5 N.C. 6 GND2B 7 GND2A 8 VCC2A 9 OUT2A ...
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... STA328 Table 2. Pin list Number 15 I I/O 18 I/O 19 I I I/O 34 I/O 35 I/O 36 I/O 2.3 Pin description OUT1A, 1B, 2A and 2B (pins 16, 10, 9 and 3) Output half bridge PWM outputs 1A, 1B, 2A and 2B provide the input signals to the speakers. RESET (pin 22) Driving RESET low sets all outputs low and returns all register settings to their default (reset) values ...
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... The left/right clock input is for data word framing. The clock frequency is at the input sample rate, fs. 10/ Clock) pins operate according to the I gives more information). Fast-mode (400 kB/s) I Figure 5 on page 7 shows the recommended circuit left or right justified, LSB or MSB first, with word widths STA328 2 C specification 2 C communication is ...
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... STA328 3 Electrical specifications Table 3. Absolute maximum ratings Symbol V 3.3 V I/O power supply (pins VDDA, VDD) DD33 V Voltage on input pins i V Voltage on output pins o T Storage temperature stg T Ambient operating temperature amb V DC supply voltage (pins VCCnA, VCCnB Maximum voltage on VL (pin 20) MAX Table 4 ...
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... Resistive load, and Figure 8 Resistive load, and Figure 3 3 Pin PWRDN = 3-state CC Min. Typ. Max. 0.8 2.0 0.4 0.15 V DD33 - 0. 25° C unless CC amb Min. Typ. Max. 200 270 Figure 8 100 100 Figure 7 25 Figure 0.8 1 STA328 Unit Unit mΩ µ ...
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... STA328 Table 8. Power electrical characteristics (continued) Symbol Supply current from V operation I VCC (both channel switching) Overcurrent protection I threshold (short circuit current out-sh limit) Undervoltage protection V UV threshold t Output minimum pulse width pw-min Output power (refer to test P o circuit Output power (refer to test ...
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... Vcc = 36 V Vcc = Ω Ω kHz kHz 0.5 0.5 0.2 0.2 0.1 0.1 0.05 0.05 0.02 0.02 0.01 0.01 100m 100m 200m 200m 500m 500m 10k 10k 20k 20k (W) Po (W) STA328 ...
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... STA328 Figure 11. THD vs output power - BTL THD (%) THD (%) Figure 12. THD vs frequency - BTL THD (%) THD (%) Vcc = 36 V Vcc = Ω Ω kHz kHz 0.5 0.5 0.2 0.2 0.1 0.1 0.05 0.05 0.02 0.02 0.01 0.01 100m 100m 200m 200m 500m 500m 0.5 0.5 ...
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... STA328 and the bus master. Data input During the data input the STA328 samples the SDA signal on the rising edge of clock SCL. For correct device operation the SDA signal must be stable during the rising edge of the clock and the data can change only when the SCL line is low. ...
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... START Current address byte read Following the START condition the master sends a device select code with the RW bit set to 1. The STA328 acknowledges this and then responds by sending one byte of data. The master then terminates the transfer by generating a STOP condition. ACK ...
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... After receiving, the internal byte address the STA328 again responds with an acknowledgement. The master then initiates another START condition and sends the device select code with the RW bit set to 1. The STA328 acknowledges this and then responds by sending one byte of data. The master then terminates the transfer by generating a STOP condition ...
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... STA328 6 Register description You must not reprogram the register bits marked “Reserved” important that these bits keep their default reset values. Table 9. Register summary Address Name D7 0x00 ConfA FDRB 0x01 ConfB C2IM 0x02 ConfC Reserved CSZ4 0x03 ConfD MME 0x04 ...
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... The STA328 will support sample rates of 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, and 96 kHz. Therefore the internal clock will be: " 32.768 MHz for 32 kHz " 45.1584 MHz for 44.1 kHz, 88.2 kHz, and 176.4 kHz " 49.152 MHz for 48 kHz, 96 kHz, and 192 kHz The external clock frequency provided to the XTI pin must be a multiple of the input sample frequency (fs) ...
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... R/W RST 4 The STA328 has variable interpolation (re-sampling) settings such that internal processing ® and DDX output rates remain consistent. The first processing block interpolates by either 2 times or 1 time (pass-through) or provides a down-sample by a factor of 2. The IR bits determine the re-sampling ratio of this interpolation. ...
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... RW 1 The on-chip STA328 power output block provides feedback to the digital controller using inputs to the power control block. The TWARN input is used to indicate a thermal warning condition. When TWARN is asserted (set to 0) for a period greater than 400 ms, the power control block will force an adjustment to the modulation limit in an attempt to eliminate the thermal warning condition ...
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... The STA328 serial audio input was designed to interface with standard digital audio components and to accept a number of serial data formats. The STA328 always acts as a slave when receiving audio input from standard digital audio components. Serial data for two channels is provided using 3 input pins: left/right clock LRCKI (pin 31), serial clock BICKI (pin 32), and serial data SDI (pin 30) ...
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... S 20-bit data 18-bit data 2 0 MSB first I S 16-bit data 2 1 LSB first I S 16-bit data X Left-justified 24-bit data X Left-justified 20-bit data X Left-justified 18-bit data X Left-justified 16-bit data X Right-justified 24-bit data X Right-justified 20-bit data X Right-justified 18-bit data X Right-justified 16-bit data STA328 ...
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... STA328 Table 19. Serial input data timing characteristics ( 192 kHz) BICKI frequency (slave mode) BICKI pulse width low (T0) (slave mode) BICKI pulse width high (T1) (slave mode) BICKI active to LRCKI edge delay (T2) BICKI active to LRCKI edge delay (T3) SDI valid to BICKI active setup (T4) BICKI active to SDI hold time (T5) Figure 16 ...
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... CSZ1 CSZ0 OM1 Description ® output. ® output timing is configured. Different ® compensating pulse. Output stage - mode Compensating pulse size STA328 D0 OM0 0 ...
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... Bypass, Bit D2, CFA) bit must be set to 0 for de-emphasis to function. Table 27. DSP bypass Bit R/W RST Setting the DSPB bit bypasses all the EQ and mixing functionality of the STA328 core. Table 28. Post-scale link Bit R/W RST Post-scale functionality is an attenuation placed after the volume control and directly before the conversion to PWM ...
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... Name Zero detect mute enable: setting of 1 enables the ZDE automatic zero-detect mute Name Miami mode enable: MME 0: sub mix into left/right disabled 1: sub mix into left/right enabled STA328 Description Description Description Description ...
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... RST The STA328 features a DDX generated in the frequency range of AM radio. This mode is intended for use when DDX operating in a device with an active AM tuner. The SNR of the DDX to approximately this mode, which is still greater than the SNR of AM radio. Table 36. ...
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... RW 1 The STA328 includes a soft volume algorithm that will step through the intermediate volume values at a predetermined rate when a volume change occurs. By setting SVE = 0 this can be bypassed and volume changes will jump from old to new value directly. This feature is only available if individual channel volume bypass bit is set to 0. ...
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... STA328 6.6 Configuration register F (addr 0x05 EAPD PWDN 0 Table 40. Output configuration selection Bit R/W RST 1 Table 41. Output configuration selection OCFG[1: Table 42. Invalid input detect mute enable Bit R/W RST Setting the IDE bit enables this function, which looks at the input I will automatically mute all outputs if the signals are perceived as invalid. ...
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... EAPD circa 260 ms later 1: normal operation Name External amplifier power down: EAPD 0: external power stage power down active 1: normal operation ® power device for normal operation. STA328 Description Description Description ® power device. This register has to ...
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... Volume description The volume structure of the STA328 consists of individual volume registers for each of the three channels and a master volume register, and individual channel volume trim registers. The channel volume settings are normally used to set the maximum allowable digital gain and to hard-set gain differences between certain channels. These values are normally set at the initialization of the IC and not changed ...
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... When ZCE = 0, volume updates will occur immediately. The STA328 also features a soft-volume update function that will ramp the volume between intermediate values when the value is updated, when SVE = 1 (configuration register E). ...
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... STA328 6.8 AutoMode registers 6.8.1 AutoModes EQ, volume, GC (addr 0x0B AMPS Reserved 1 0 Table 49. AutoMode EQ AMEQ[1, setting AMEQ to any setting other than 00 enables AutoMode EQ where biquads 1-4 are not user programmable. Any coefficient settings for these biquads are ignored. Also when AutoMode EQ is used the pre-scale value for channels 1-2 becomes hard-set to -18 dB. ...
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... Name AutoMode crossover frequency selection 000: user defined crossover coefficients are used XO[3:0] Otherwise: preset coefficients for the crossover setting desired Bass management - Crossover frequency User 80 Hz 100 Hz 120 Hz 140 Hz STA328 AMAM1 AMAM0 AMAME Description 44.1 kHz/88.2 kHz input fs 0.535 MHz -0.670 MHz ...
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... STA328 Table 56. Crossover frequency selection (continued) XO[2:0] 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 6.8.3 Preset EQ settings (addr 0x0D Reserved Reserved 0 0 Table 57. Preset EQ selection PEQ[3:0] 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 ...
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... Loudness 2 Loudness 3 Loudness 4 Loudness 5 Loudness 6 Loudness 7 Loudness 8 Loudness 9 Loudness 10 Loudness 11 Loudness 12 Loudness 13 Loudness 14 Loudness 15 Loudness 16 (most boost C1LS1 C1LS0 C2LS1 C2LS0 C3LS1 C3LS0 0 0 Setting C1BO C1VBP C1EQBP C2BO C2VBP C2EQBP C3BO C3VBP Reserved STA328 D0 C1TCB 0 D0 C2TCB 0 D0 Reserved 0 ...
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... PWM encoded data. By setting the CxBO bit to 1, each channel can be individually controlled binary operation mode. Also, there is the capability to map each channel independently onto any of the two limiters available within the STA328 or even not map it to any limiter at all (default mode). Table 58. Channel limiter mapping selection ...
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... Tone control (addr 0x11 TTC3 TTC2 0 1 Table 60. Tone control boost/cut selection BTC[3:0]/TTC[3:0] 0000 0001 … 0111 0110 0111 1000 1001 … 1101 1110 1111 40/ TTC1 TTC0 BTC3 -12 dB -12 dB … … +12 dB +12 dB +12 dB STA328 BTC2 BTC1 BTC0 Boost/Cut ...
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... Dynamics control description The STA328 includes 2 independent limiter blocks. The purpose of the limiters is to automatically reduce the dynamic range of a recording to prevent the outputs from clipping in anti-clipping mode actively reduce the dynamic range for a better listening environment (such as a night-time listening mode, which is often needed for DVDs.) The two modes are selected via the DRC bit in configuration register D (bit 5, address 0x03) ...
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... Slow 1111 RMS Output Saturation Release rate LxR[3:0] dB/ms 0.5116 0.1370 0.0744 0.0499 0.0360 0.0299 0.0264 0.0208 0.0198 0.0172 0.0147 0.0137 0.0134 0.0117 0.0110 0.0104 STA328 ...
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... STA328 6.11.6 Anti-clipping mode Table 62. Limiter attack/release threshold selection (AC mode) LxAT[3:0] 0000 -12 0001 -10 0010 -8 0011 -6 0100 -4 0101 -2 0110 0 0111 +2 1000 +3 1001 +4 1010 +5 1011 +6 1100 +7 1101 +8 1110 +9 1111 +10 Attack threshold (AC) dB relative to FS 0000 0001 0010 0011 0100 0101 0110 0111 1000 ...
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... Release threshold (DRC) LxRT[3:0] db relative to volume + LxAT -∞ 0000 0001 -38 dB 0010 -36 dB 0011 -33 dB 0100 -31 dB 0101 -30 dB 0110 -28 dB 0111 -26 dB 1000 -24 dB 1001 -22 dB 1010 -20 dB 1011 -18 dB 1100 -15 dB 1101 -12 dB 1110 -9 dB 1111 -6 dB STA328 ...
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... Post-scale The STA328 provides one additional multiplication after the last interpolation stage and before the distortion compensation on each channel. This is a 24-bit signed fractional multiplier. The scale factor for this multiplier is loaded into RAM using the same I as the biquad coefficients and the mix. All channels can use the same settings as channel 1 by setting the post-scale link bit ...
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... User programmable processing 7.4 Mix/bass management The STA328 provides a post-EQ mixing block per channel. Each channel has 2 mixing coefficients, which are each 24-bit signed fractional multipliers, that correspond to the 2 channels of input to the mixing block. These coefficients are accessible via the user controlled coefficient RAM described below. The mix coefficients are expressed as 24-bit signed ...
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... Calculating 24-bit signed fractional numbers from a dB value The pre-scale, mixing, and post-scale functions of the STA328 use 24-bit signed fractional multipliers to attenuate signals. These attenuations can also invert the phase and therefore range in value from - possible to calculate the coefficient to utilize for a given negative dB value (attenuation) via the equations below. " ...
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... D2 D1 C2B11 C2B10 C2B9 C2B3 C2B2 C2B1 C1B19 C1B18 C1B17 C3B11 C3B10 C3B9 C3B3 C3B2 C3B1 C4B19 C4B18 C4B17 C4B11 C4B10 C4B9 C4B3 C4B2 C4B1 STA328 D0 C2B8 0 D0 C2B0 0 D0 C1B16 0 D0 C3B8 0 D0 C3B0 0 D0 C4B16 0 D0 C4B8 0 D0 C4B0 0 ...
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... Reserved Reserved 0 Coefficients for EQ, mix and scaling are handled internally in the STA328 via RAM. Access to this RAM is available to the user via an I are dedicated to this function. First register contains the coefficient base address, five sets of three registers store the values of the 24-bit coefficients to be written or that were read, and one contains bits used to control the read or write of the coefficient (s) to RAM ...
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... C address 0x1D 2 C address 0x1E 2 C address 0x1F 2 C address 0x20 2 C address 0x21 2 C address 0x22 2 C address 0x23 2 C address 0x24 2 C address 0x25 2 C register 0x16 2 C address 0x17 2 C address 0x18 2 C address 0x19 2 C address 0x26 STA328 ...
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... When using this technique, the 8-bit address would specify the address of the biquad b1 coefficient (for example 0, 5, 10, 15, …, 45 decimal), and the STA328 will generate the RAM addresses as offsets from this base value to write the complete set of coefficient data. ...
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... Channel 1 - Mix 1 0x39 Channel 1 - Mix 2 0x3A Channel 2 - Mix 1 0x3B Channel 2 - Mix 2 0x3C Channel 3 - Mix 1 0x3D Channel 3 - Mix 2 0x3E Unused 0x3F Unused STA328 Coefficient Default C12H0 (b1/2) 0x000000 C12H1 (b2) 0x000000 C12H2 (a1/2) 0x000000 C12H3 (a2) 0x000000 C12H4 (b0/2) 0x400000 C12L0 (b1/2) 0x000000 C12L1 (b2) ...
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... STA328 7.11 Variable max power correction (addr 0x27, 0x28 MPCC15 MPCC14 0 MPCC7 MPCC6 1 MPCC bits determine the 16 MSBs of the MPC compensation coefficient. This coefficient is used in place of the default coefficient when MPCV = 1. 7.12 Fault detect recovery (addr 0x2B, 0x2C FRDC15 FDRC14 0 0 FDRC7 ...
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... Package mechanical data 8 Package mechanical data Figure 20. PowerSO-36 slug up outline drawing 54/57 STA328 ...
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... STA328 Table 65. PowerSO-36 slug up dimensions Symbol Min A 3.25 A2 3. 0.03 b 0.22 c 0.23 D 15. 13.90 E1 10. 5. 15. 0. order to meet environmental requirements, ST offers these devices in ECOPACK packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97 ...
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... Updated applications schematic Added characterization curves in Updated device address in 4 Updated configuration registers in page 19 Updated configuration registers from Section 6.5 Updated PowerSO-36 Changes Figure 5 on page 7 Chapter 4 on page 14 Section 5.2 on page 16 Table 9: Register summary on Section 6.1 on page 20 Package mechanical data on page 54 STA328 to ...
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... STA328 Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...