SST25VF016B-75-4I-S2AF SILICON STORAGE TECHNOLOGY, SST25VF016B-75-4I-S2AF Datasheet - Page 9

• Manufacturer Part Number: SST25VF016B-75-4I-S2AF
• Description: MEMORY, FLASH, 16MBIT, SPI, 8SOIC
• Manufacturer: SILICON STORAGE TECHNOLOGY

Specifications of SST25VF016B-75-4I-S2AF

• Memory Size: 16Mbit
• Clock Frequency: 75MHz
• Supply Voltage Range: 2.7V To 3.6V
• Memory Case Style: SOIC
• No. Of Pins: 8
• Operating Temperature Range: -40°C To +85°C
• Svhc: No SVHC (18-Jun-2010)
• Memory Type: Flash
• Memory Configuration: 2M X 8
• Interface Type: Serial, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

A Microchip Technology Company
©2011 Silicon Storage Technology, Inc.
Instructions
Instructions are used to read, write (Erase and Program), and configure the SST25VF016B. The
instruction bus cycles are 8 bits each for commands (Op Code), data, and addresses. Prior to execut-
ing any Byte-Program, Auto Address Increment (AAI) programming, Sector-Erase, Block-Erase, Write-
Status-Register, or Chip-Erase instructions, the Write-Enable (WREN) instruction must be executed
first. The complete list of instructions is provided in Table 5. All instructions are synchronized off a high
to low transition of CE#. Inputs will be accepted on the rising edge of SCK starting with the most signif-
icant bit. CE# must be driven low before an instruction is entered and must be driven high after the last
bit of the instruction has been shifted in (except for Read, Read-ID, and Read-Status-Register instruc-
tions). Any low to high transition on CE#, before receiving the last bit of an instruction bus cycle, will
terminate the instruction in progress and return the device to standby mode. Instruction commands
(Op Code), addresses, and data are all input from the most significant bit (MSB) first.
Table 5: Device Operation Instructions
Instruction
Read
High-Speed
Read
4 KByte Sec-
tor-Erase
32 KByte
Block-Erase
64 KByte
Block-Erase
Chip-Erase
Byte-Program
AAI-Word-Pro-
gram
RDSR
EWSR
WRSR
WREN
WRDI
RDID
JEDEC-ID
EBSY
DBSY
1. One bus cycle is eight clock periods.
6
8
7
3
4
5
Description
Read Memory at 25 MHz
Read Memory at 80 MHz
Erase 4 KByte of
memory array
Erase 32 KByte block
of memory array
Erase 64 KByte block
of memory array
Erase Full Memory Array
To Program One Data Byte 0000 0010b (02H)
Auto Address Increment
Programming
Read-Status-Register
Enable-Write-Status-Reg-
ister
Write-Status-Register
Write-Enable
Write-Disable
Read-ID
JEDEC ID read
Enable SO to output RY/BY#
status during AAI program-
ming
Disable SO as RY/BY#
status during AAI program-
ming
9
Op Code Cycle
0000 0011b (03H)
0000 1011b (0BH)
0010 0000b (20H)
0101 0010b (52H)
1101 1000b (D8H)
0110 0000b (60H)
or
1100 0111b (C7H)
1010 1101b (ADH)
0000 0101b (05H)
0101b 0000b
(50H)
0000 0001b (01H)
0000 0110b (06H)
0000 0100b (04H)
1001 0000b (90H)
or
1010 1011b (ABH)
1001 1111b (9FH)
0111 0000b (70H)
1000 0000b (80H)
16 Mbit SPI Serial Flash
1
Cycle(s)
Address
3
3
3
3
3
0
3
3
0
0
0
0
0
3
0
0
0
2
Cycle(s)
Dummy
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SST25VF016B
Cycle(s)
1 to ∞
1 to ∞
2 to ∞
1 to ∞
1 to ∞
3 to ∞
Data
0
0
0
0
1
0
1
0
0
0
0
S71271-04-000
Data Sheet
Frequency
Maximum
25 MHz
80 MHz
80 MHz
80 MHz
80 MHz
80 MHz
80 MHz
80 MHz
80 MHz
80 MHz
80 MHz
80 MHz
80 MHz
80 MHz
80 MHz
80 MHz
80 MHz
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