SST25VF016B-75-4I-S2AF SILICON STORAGE TECHNOLOGY, SST25VF016B-75-4I-S2AF Datasheet - Page 11

• Manufacturer Part Number: SST25VF016B-75-4I-S2AF
• Description: MEMORY, FLASH, 16MBIT, SPI, 8SOIC
• Manufacturer: SILICON STORAGE TECHNOLOGY

Specifications of SST25VF016B-75-4I-S2AF

• Memory Size: 16Mbit
• Clock Frequency: 75MHz
• Supply Voltage Range: 2.7V To 3.6V
• Memory Case Style: SOIC
• No. Of Pins: 8
• Operating Temperature Range: -40°C To +85°C
• Svhc: No SVHC (18-Jun-2010)
• Memory Type: Flash
• Memory Configuration: 2M X 8
• Interface Type: Serial, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

A Microchip Technology Company
©2011 Silicon Storage Technology, Inc.
High-Speed-Read (80 MHz)
Byte-Program
The High-Speed-Read instruction supporting up to 80 MHz Read is initiated by executing an 8-bit com-
mand, 0BH, followed by address bits [A
duration of the High-Speed-Read cycle. See Figure 6 for the High-Speed-Read sequence.
Following a dummy cycle, the High-Speed-Read instruction outputs the data starting from the speci-
fied address location. The data output stream is continuous through all addresses until terminated by a
low to high transition on CE#. The internal address pointer will automatically increment until the high-
est memory address is reached. Once the highest memory address is reached, the address pointer
will automatically increment to the beginning (wrap-around) of the address space. Once the data from
address location 1FFFFFH has been read, the next output will be from address location 000000H.
Figure 6: High-Speed-Read Sequence
The Byte-Program instruction programs the bits in the selected byte to the desired data. The selected
byte must be in the erased state (FFH) when initiating a Program operation. A Byte-Program instruction
applied to a protected memory area will be ignored.
Prior to any Write operation, the Write-Enable (WREN) instruction must be executed. CE# must remain
active low for the duration of the Byte-Program instruction. The Byte-Program instruction is initiated by
executing an 8-bit command, 02H, followed by address bits [A
input in order from MSB (bit 7) to LSB (bit 0). CE# must be driven high before the instruction is exe-
cuted. The user may poll the Busy bit in the software status register or wait T
the internal self-timed Byte-Program operation. See Figure 7 for the Byte-Program sequence.
Figure 7: Byte-Program Sequence
SCK
CE#
SO
SI
MODE 3
MODE 0
Note: X = Dummy Byte: 8 Clocks Input Dummy Cycle (V
MSB
0 1 2 3 4 5 6 7 8
SCK
CE#
SO
SI
0B
MODE 3
MODE 0
HIGH IMPEDANCE
MSB
0 1 2 3 4 5 6 7 8
MSB
ADD.
02
15 16
11
23
ADD.
-A
0
HIGH IMPEDANCE
] and a dummy byte. CE# must remain active low for the
23 24
MSB
ADD.
IL
ADD.
or V
31 32
IH
15 16
)
16 Mbit SPI Serial Flash
X
ADD.
39 40
MSB
23
23 24
D
-A
OUT
N
0
ADD.
]. Following the address, the data is
47 48
31 32
D
N+1
OUT
MSB
1271 ByteProg.0
55 56
D
IN
LSB
D
SST25VF016B
BP
39
N+2
OUT
for the completion of
63 64
D
N+3
S71271-04-000
OUT
71 72
1271 HSRdSeq.0
Data Sheet
D
N+4
OUT
80
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