SST25VF016B-75-4I-QAF SILICON STORAGE TECHNOLOGY, SST25VF016B-75-4I-QAF Datasheet
SST25VF016B-75-4I-QAF
Specifications of SST25VF016B-75-4I-QAF
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SST25VF016B-75-4I-QAF Summary of contents
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... SST's 25 series Serial Flash family features a four-wire, SPI-compatible inter- face that allows for a low pin-count package which occupies less board space and ultimately lowers total system costs. The SST25VF016B devices are enhanced with improved operating frequency which lowers power consump- tion. SST25VF016B SPI serial flash memories are manufactured with SST's proprietary, high-performance CMOS SuperFlash technology ...
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... Erase or Program operation is less than alternative flash memory technologies. The SST25VF016B device is offered in both 8-lead SOIC (200 mils) and 8-contact WSON (6mm x 5mm) packages. See Figure 2 for pin assignments. ...
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... Block Diagram Figure 1: Functional Block Diagram ©2011 Silicon Storage Technology, Inc. 16 Mbit SPI Serial Flash X - Decoder Address Buffers and Latches Control Logic Serial Interface CE# SCK SST25VF016B Data Sheet SuperFlash Memory Y - Decoder I/O Buffers and Data Latches WP# HOLD# 1271 B1.0 S71271-04-000 01/11 ...
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... The Write Protect (WP#) pin is used to enable/disable BPL bit in the status regis- ter. To temporarily stop serial communication with SPI flash memory without resetting the device. To provide power supply voltage: 2.7-3.6V for SST25VF016B 4 16 Mbit SPI Serial Flash SST25VF016B Data Sheet ...
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... Serial Data Input (SI), Serial Data Output (SO), and Serial Clock (SCK). The SST25VF016B supports both Mode 0 (0,0) and Mode 3 (1,1) of SPI bus operations. The difference between the two modes, as shown in Figure 3, is the state of the SCK signal when the bus master is in Stand-by mode and no data is being transferred ...
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... Figure 4: Hold Condition Waveform Write Protection SST25VF016B provides software Write protection. The Write Protect pin (WP#) enables or disables the lock-down function of the status register. The Block-Protection bits (BP3, BP2, BP1, BP0, and BPL) in the status register provide Write protection to the memory array and the status register. See Table 4 for the Block-Protection description ...
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... Indicate current level of block write protection (See Table 4) Indicate current level of block write protection (See Table 4) Auto Address Increment Programming status 1 = AAI programming mode 0 = Byte-Program mode 1 = BP3, BP2, BP1, BP0 are read-only bits 0 = BP3, BP2, BP1, BP0 are read/writable 7 SST25VF016B Data Sheet Default at Power-up Read/Write ...
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... BPL, BP3, BP2, BP1, and BP0 bits. When the WP# pin is driven high (V ), the BPL bit has no effect and its value is “Don’t Care”. After power-up, the BPL bit is reset Table 4: Software Status Register Block Protection for SST25VF016B Protection Level None Upper 1/32 Upper 1/16 ...
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... A Microchip Technology Company Instructions Instructions are used to read, write (Erase and Program), and configure the SST25VF016B. The instruction bus cycles are 8 bits each for commands (Op Code), data, and addresses. Prior to execut- ing any Byte-Program, Auto Address Increment (AAI) programming, Sector-Erase, Block-Erase, Write- Status-Register, or Chip-Erase instructions, the Write-Enable (WREN) instruction must be executed first ...
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... with A = =0, and Device ID is read with ADD. ADD. ADD. MSB HIGH IMPEDANCE 10 16 Mbit SPI Serial Flash SST25VF016B with A =0, Data Byte 1 will =1. All other address bits are 00H. The Manufac N+1 N+2 N+3 ...
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... CE# must remain active low for the ADD. ADD. ADD. MSB HIGH IMPEDANCE CE# MODE MODE 0 SCK 02 ADD. SI MSB MSB HIGH IMPEDANCE Mbit SPI Serial Flash SST25VF016B N+1 N+2 N OUT OUT OUT OUT MSB ) 1271 HSRdSeq Following the address, the data for the completion of ...
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... Enable-Latch bit (WEL=0) and AAI bit. Then execute the 8-bit DBSY command, 80H, to disable RY/ BY# status during the AAI command. See Figures 9 and 10. ©2011 Silicon Storage Technology, Inc. 16 Mbit SPI Serial Flash -A ] with The Hardware End-of-Write detection method is described in the BP. 12 SST25VF016B Data Sheet BP Fol with A =0, the second 23 ...
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... Figure 8: Enable SO as Hardware RY/BY# During AAI Programming Figure 9: Disable SO as Hardware RY/BY# During AAI Programming ©2011 Silicon Storage Technology, Inc. 16 Mbit SPI Serial Flash CE# MODE SCK MODE MSB HIGH IMPEDANCE SO 1271 EnableSO.0 CE# MODE MODE 0 SCK 80 SI MSB HIGH IMPEDANCE SO 1271 DisableSO.0 13 SST25VF016B Data Sheet S71271-04-000 01/11 ...
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... Check for Flash Busy Status to load next valid 1. Valid commands during AAI programming: AAI command or WRDI command 2. User must configure the SO pin to output Flash Busy status during AAI programming Wait T register to load next valid Mbit SPI Serial Flash SST25VF016B Check for Flash Busy Status to load next valid command ...
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... Silicon Storage Technology, Inc. 16 Mbit SPI Serial Flash -A ]. Address bits [ remaining address bits can CE# MODE MODE 0 SCK 20 ADD. SI MSB MSB HIGH IMPEDANCE SO 15 SST25VF016B Data Sheet = Most Significant address) are used CE# must be driven high IL IH ADD. ADD. 1271 SecErase.0 S71271-04-000 01/11 ...
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... CE# must be driven high before the instruction is executed. The 64-Kbyte Block- IL IH. ), remaining address bits can CE# MODE MODE 0 SCK 52 SI MSB HIGH IMPEDANCE SO CE# MODE MODE 0 SCK D8 SI MSB HIGH IMPEDANCE Mbit SPI Serial Flash SST25VF016B - Address bits IH ADDR ADDR ADDR MSB 1271 32KBklEr ADDR ADDR ADDR MSB 1271 63KBlkEr.0 ...
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... Figure 16:Read-Status-Register (RDSR) Sequence ©2011 Silicon Storage Technology, Inc. CE# MODE SCK MODE MSB HIGH IMPEDANCE MSB HIGH IMPEDANCE 17 16 Mbit SPI Serial Flash SST25VF016B Data Sheet 1271 ChEr Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MSB Status Register Out 1271 RDSRseq.0 S71271-04-000 01/11 ...
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... CE# must be driven high before the WRDI instruction is executed. Figure 18:Write Disable (WRDI) Sequence ©2011 Silicon Storage Technology, Inc. 16 Mbit SPI Serial Flash CE# MODE MODE 0 SCK 06 SI MSB HIGH IMPEDANCE SO 1271 WREN.0 CE# MODE SCK MODE MSB HIGH IMPEDANCE SO 1271 WRDI.0 18 SST25VF016B Data Sheet after executing the WRDI BP S71271-04-000 01/11 ...
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... Figure 19:Enable-Write-Status-Register (EWSR) or Write-Enable (WREN) and Write-Status-Register (WRSR) Sequence ©2011 Silicon Storage Technology, Inc. ) prior to the low-to-high transition of the CE# pin at the end MODE 3 MODE MSB MSB HIGH IMPEDANCE 19 16 Mbit SPI Serial Flash SST25VF016B Data Sheet STATUS REGISTER MSB 1271 EWSR.0 S71271-04-000 01/11 ...
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... Read-ID instruction, the 8-bit manufacturer’s ID, BFH, is output from the device. After that, a 16-bit device ID is shifted out on the SO pin. Byte 1, BFH, identifies the manufacturer as SST. Byte 2, 25H, identifies the memory type as SPI Serial Flash. Byte 3, 41H, identifies the device as SST25VF016B. The instruction sequence is shown in Figure 20. The JEDEC Read ID instruction is terminated by a low to high transition on CE# at any time during data output ...
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... A Microchip Technology Company Read-ID (RDID) The Read-ID instruction (RDID) identifies the devices as SST25VF016B and manufacturer as SST. This command is backward compatible to all SST25xFxxxA devices and should be used as default device identification when multiple versions of SPI Serial Flash devices are used in a design. The ...
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... Ambient Temp 0°C to +70°C -40°C to +85°C 1 Input Rise/Fall Time 5ns 22 16 Mbit SPI Serial Flash SST25VF016B Data Sheet 2.7-3.6V 2.7-3.6V Output Load ...
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... Min to Write Operation 25°C, f=1 Mhz, other pins open) A Description Output Pin Capacitance Input Capacitance Parameter Minimum Specification Endurance Data Retention Latch Mbit SPI Serial Flash SST25VF016B Test Conditions mA CE#=0.1 V /0.9 V @25 MHz, SO=open CE#=0.1 V /0.9 V @50 MHz, SO=open CE#=0 ...
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... Maximum Rise and Fall time may be limited Relative to SCK. ©2011 Silicon Storage Technology, Inc. 16 Mbit SPI Serial Flash 25 MHz Parameter Min Max 0.1 0 100 and T requirements SCKH SCKL 24 SST25VF016B Data Sheet 50 MHz 80 MHz Min Max Min Max Units 50 80 MHz 0.1 0.1 V/ns 0.1 0.1 V/ ...
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... SO SI Figure 23:Serial Output Timing Diagram ©2011 Silicon Storage Technology, Inc. T CES SCKR MSB HIGH SCKH SCKL CLZ MSB Mbit SPI Serial Flash SST25VF016B Data Sheet T CPH T T CEH CHS T SCKF LSB HIGH-Z T CHZ LSB 1271 SerOut.0 S71271-04-000 1271 SerIn.0 01/11 ...
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... Silicon Storage Technology, Inc HHH HLS T HZ Chip selection is not allowed. Commands may not be accepted or properly interpreted by the device. T PU-READ T PU-WRITE 26 16 Mbit SPI Serial Flash SST25VF016B Data Sheet T HHS T HLH T LZ 1271 Hold.0 Device fully accessible Time 1271 PwrUp.0 S71271-04-000 01/11 ...
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... INPUT REFERENCE POINTS V LT (0.9V ) for a logic “1” and V IHT DD ↔ 90%) are <5 ns. TO TESTER TO DUT 27 16 Mbit SPI Serial Flash SST25VF016B Data Sheet V HT OUTPUT V LT 1271 IORef.0 (0.1V ) for a logic “0”. Mea- ILT DD (0.6V ) and V (0.4V ). Input rise ...
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... S2AF XXXX - XXXX SST25VF016B-50-4C-QAF SST25VF016B-50-4I-QAF SST25VF016B-75-4I-QAF 28 16 Mbit SPI Serial Flash SST25VF016B Data Sheet Environmental Attribute non-Pb / non-Sn contact (lead) finish: Nickel plating with Gold top (outer) layer Package Modifier leads or contacts Package Type S2 = SOIC 200 mil body width Q = WSON Temperature Range C = Commercial = 0° ...
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... SST Package Code: S2A ©2011 Silicon Storage Technology, Inc. TOP VIEW SIDE VIEW 5.40 5.15 2.16 8.10 1.75 7.70 0.25 0. Mbit SPI Serial Flash SST25VF016B Data Sheet 0.50 0.35 1.27 BSC 0.25 END VIEW 0.05 08-soic-EIAJ-S2A-3 1mm S71271-04-000 0° 8° 0.80 ...
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... Silicon Storage Technology, Inc. TOP VIEW SIDE VIEW 5.00 0 .10 6.00 0.10 0.80 0.70 leads the unit Mbit SPI Serial Flash SST25VF016B BOTTOM VIEW 0.2 4.0 0.076 3.4 0.05 Max CROSS SECTION 1mm 8-wson-5x6-QA-9.0 S71271-04-000 Data Sheet Pin #1 1.27 BSC ...
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... For sales office(s) location and information, please see www.microchip.com or www.sst.com. ©2011 Silicon Storage Technology, Inc. 16 Mbit SPI Serial Flash Description and V values in Figure 26 on page Silicon Storage Technology, Inc. A Microchip Technology Company www.microchip.com or www.sst.com 31 SST25VF016B Data Sheet Date Apr 2005 Sep 2005 Jan 2006 Sep 2008 Jan 2011 S71271-04-000 01/11 ...