PIC18LF6680-I/L Microchip Technology, PIC18LF6680-I/L Datasheet - Page 345
![IC, 8BIT MCU, PIC18LF, 40MHZ, PLCC-64](/photos/12/13/121323/c04-049_l_sml.jpg)
PIC18LF6680-I/L
Manufacturer Part Number
PIC18LF6680-I/L
Description
IC, 8BIT MCU, PIC18LF, 40MHZ, PLCC-64
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PCM18XK1.pdf
(496 pages)
3.PIC18F6585-IPT.pdf
(8 pages)
4.PIC18F6585-IPT.pdf
(38 pages)
5.PIC18F6585-IPT.pdf
(14 pages)
Specifications of PIC18LF6680-I/L
Controller Family/series
PIC18
No. Of I/o's
53
Eeprom Memory Size
1024Byte
Ram Memory Size
3328Byte
Cpu Speed
40MHz
No. Of Timers
4
Core Size
8 Bit
Program Memory Size
32768 Words
Core Processor
PIC
Speed
40MHz
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
52
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
3.25K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
68-PLCC
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3328 B
Interface Type
I2C, SPI, AUSART, CAN
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
53
Number Of Timers
8
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18LF6680-I/L
Manufacturer:
MICROCHIP
Quantity:
3 000
- PIC16F616T-ISL PDF datasheet
- PCM18XK1 PDF datasheet #2
- PIC18F6585-IPT PDF datasheet #3
- PIC18F6585-IPT PDF datasheet #4
- PIC18F6585-IPT PDF datasheet #5
- Current page: 345 of 496
- Download datasheet (9Mb)
23.15.2
When the transmit interrupt is enabled, an interrupt will
be generated when the associated transmit buffer
becomes empty and is ready to be loaded with a new
message. In Mode 0, there are separate interrupt
enable/disable and flag bits for each of the three
dedicated transmit buffers. The TXBnIF bit will be set to
indicate the source of the interrupt. The interrupt is
cleared by the MCU resetting the TXBnIF bit to a ‘0’. In
Mode 1 and 2, all transmit buffers share one interrupt
enable/disable and flag bits. In Mode 1 and 2, TXBIE in
PIE3 and TXBIF in PIR3 indicate when a transmit buffer
has completed transmission of its message. TXBnIF,
TXBnIE and TXBnIP in PIR3, PIE3 and IPR3, respec-
tively, are not used in Mode 1 and 2. Individual transmit
buffer interrupts can be enabled or disabled by setting or
clearing TXBIE and BnIE register bits. When a shared
interrupt occurs, user firmware must poll the TXREQ bit
of all transmit buffers to detect the source of interrupt.
23.15.3
When the receive interrupt is enabled, an interrupt will
be generated when a message has been successfully
received and loaded into the associated receive buffer.
This interrupt is activated immediately after receiving
the End Of Frame (EOF) field.
In Mode 0, the RXBnIF bit is set to indicate the source
of the interrupt. The interrupt is cleared by the MCU
resetting the RXBnIF bit to a ‘0’.
In Mode 1 and 2, all receive buffers share one interrupt.
Individual receive buffer interrupts can be controlled by
the RXBnIE and BIEn registers. In Mode 1, when a
shared receive interrupt occurs, user firmware must
poll the RXFUL bit of each receive buffer to detect the
source of interrupt. In Mode 2, a receive interrupt
indicates that the new message is loaded into FIFO.
FIFO can be read by using FIFO pointer bits, FP.
In Mode 2, the FIFOWMIF bit indicates if the FIFO high
watermark is reached. The FIFO high watermark is
defined by the FIFOWM bit in the ECANCON register.
23.15.4
When an error occurs during transmission or reception
of a message, the message error flag, IRXIF, will be set
and if the IRXIE bit is set, an interrupt will be generated.
This is intended to be used to facilitate baud rate
determination when used in conjunction with Listen
Only mode.
2004 Microchip Technology Inc.
TRANSMIT INTERRUPT
RECEIVE INTERRUPT
MESSAGE ERROR INTERRUPT
PIC18F6585/8585/6680/8680
23.15.5
When the PIC18F6585/8585/6680/8680 devices are in
Sleep mode and the bus activity wake-up interrupt is
enabled, an interrupt will be generated and the WAKIF
bit will be set when activity is detected on the CAN bus.
This interrupt causes the PIC18F6585/8585/6680/
8680 devices to exit Sleep mode. The interrupt is reset
by the MCU, clearing the WAKIF bit.
23.15.6
When the error interrupt is enabled, an interrupt is
generated if an overflow condition occurs or if the error
state of the transmitter or receiver has changed. The
error flags in COMSTAT will indicate one of the
following conditions.
23.15.6.1
An overflow condition occurs when the MAB has
assembled a valid received message (the message
meets the criteria of the acceptance filters) and the
receive buffer associated with the filter is not available
for loading of a new message. The associated
COMSTAT.RXnOVFL bit will be set to indicate the
overflow condition. This bit must be cleared by the
MCU.
23.15.6.2
The receive error counter has reached the MCU
warning limit of 96.
23.15.6.3
The transmit error counter has reached the MCU
warning limit of 96.
23.15.6.4
The receive error counter has exceeded the error-
passive limit of 127 and the device has gone to
error-passive state.
23.15.6.5
The transmit error counter has exceeded the error-
passive limit of 127 and the device has gone to
error-passive state.
23.15.6.6
The transmit error counter has exceeded 255 and the
device has gone to bus-off state.
23.15.6.7
Interrupts are directly associated with one or more sta-
tus flags in the PIR register. Interrupts are pending as
long as one of the flags is set. Once an interrupt flag is
set by the device, the flag can not be reset by the
microcontroller until the interrupt condition is removed.
BUS ACTIVITY WAKE-UP
INTERRUPT
ERROR INTERRUPT
Receiver Overflow
Receiver Warning
Transmitter Warning
Receiver Bus Passive
Transmitter Bus Passive
Bus-Off
Interrupt Acknowledge
DS30491C-page 343
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