PIC18LF6680-I/L Microchip Technology, PIC18LF6680-I/L Datasheet - Page 339
![IC, 8BIT MCU, PIC18LF, 40MHZ, PLCC-64](/photos/12/13/121323/c04-049_l_sml.jpg)
PIC18LF6680-I/L
Manufacturer Part Number
PIC18LF6680-I/L
Description
IC, 8BIT MCU, PIC18LF, 40MHZ, PLCC-64
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PCM18XK1.pdf
(496 pages)
3.PIC18F6585-IPT.pdf
(8 pages)
4.PIC18F6585-IPT.pdf
(38 pages)
5.PIC18F6585-IPT.pdf
(14 pages)
Specifications of PIC18LF6680-I/L
Controller Family/series
PIC18
No. Of I/o's
53
Eeprom Memory Size
1024Byte
Ram Memory Size
3328Byte
Cpu Speed
40MHz
No. Of Timers
4
Core Size
8 Bit
Program Memory Size
32768 Words
Core Processor
PIC
Speed
40MHz
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
52
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
3.25K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
68-PLCC
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3328 B
Interface Type
I2C, SPI, AUSART, CAN
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
53
Number Of Timers
8
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18LF6680-I/L
Manufacturer:
MICROCHIP
Quantity:
3 000
- PIC16F616T-ISL PDF datasheet
- PCM18XK1 PDF datasheet #2
- PIC18F6585-IPT PDF datasheet #3
- PIC18F6585-IPT PDF datasheet #4
- PIC18F6585-IPT PDF datasheet #5
- Current page: 339 of 496
- Download datasheet (9Mb)
23.9.1
As already mentioned, the Time Quanta is a fixed unit
derived from the oscillator period and baud rate
prescaler. Its relationship to T
Rate is shown in Example 23-6.
EXAMPLE 23-6:
The frequencies of the oscillators in the different nodes
must be coordinated in order to provide a system wide
specified nominal bit time. This means that all oscilla-
tors must have a T
It should also be noted that although the number of T
is programmable from 4 to 25, the usable minimum is
8 T
guaranteed to operate correctly.
2004 Microchip Technology Inc.
T
T
Nominal Bit Rate (bits/s) = 1/T
CASE 1:
For F
Nominal Bit Time = 8 T
T
T
Nominal Bit Rate = 1/10
CASE 2:
For F
Nominal Bit Time = 8 T
T
T
Nominal Bit Rate = 1/1.6 * 10
CASE 3:
For F
Nominal Bit Time = 25 T
T
T
Nominal Bit Rate = 1/1.28 * 10
Q
BIT
Q
BIT
Q
BIT
Q
BIT
Q
= (2*1)/16 = 0.125 s (125 ns)
= (2*2)/20 = 0.2 s (200 ns)
= (2*64)/25 = 5.12 s
. A bit time of less than 8 T
( s) = (2 * (BRP+1))/F
( s) = T
= 8 * 0.125 = 1 s (10
= 8 * 0.2 = 1.6 s (1.6 * 10
= 25 * 5.12 = 128 s (1.28 * 10
OSC
OSC
OSC
= 16 MHz, BRP<5:0> = 00h and
= 20 MHz, BRP<5:0> = 01h and
= 25 MHz, BRP<5:0> = 3Fh and
TIME QUANTA
Q
( s) * number of T
OSC
CALCULATING T
NOMINAL BIT RATE AND
NOMINAL BIT TIME
that is an integral divisor of T
-6
Q
Q
OSC
= 10
Q
:
:
-6
:
s)
-6
(MHz)
BIT
6
-4
BIT
s = 625,000 bits/s
-6
bits/s (1 Mb/s)
= 7813 bits/s
s)
Q
(625 Kb/s)
(7.8 Kb/s)
and the Nominal Bit
per bit interval
-4
Q
s)
in length is not
Q
,
PIC18F6585/8585/6680/8680
Q
Q
.
23.9.2
This part of the bit time is used to synchronize the
various CAN nodes on the bus. The edge of the input
signal is expected to occur during the sync segment.
The duration is 1 T
23.9.3
This part of the bit time is used to compensate for phys-
ical delay times within the network. These delay times
consist of the signal propagation time on the bus line
and the internal delay time of the nodes. The length of
the Propagation Segment can be programmed from
1 T
23.9.4
The phase buffer segments are used to optimally
locate the sampling point of the received bit within the
nominal bit time. The sampling point occurs between
Phase Segment 1 and Phase Segment 2. These
segments can be lengthened or shortened by the
resynchronization process. The end of Phase Segment
1 determines the sampling point within a bit time.
Phase Segment 1 is programmable from 1 T
in duration. Phase Segment 2 provides delay before
the next transmitted data transition and is also
programmable from 1 T
due to IPT requirements, the actual minimum length of
Phase Segment 2 is 2 T
equal to the greater of Phase Segment 1 or the
Information Processing Time (IPT).
23.9.5
The sample point is the point of time at which the bus
level is read and the value of the received bit is deter-
mined. The sampling point occurs at the end of Phase
Segment 1. If the bit timing is slow and contains many
T
line at the sample point. The value of the received bit is
determined to be the value of the majority decision of
three values. The three samples are taken at the sam-
ple point and twice before, with a time of T
each sample.
23.9.6
The Information Processing Time (IPT) is the time
segment starting at the sample point that is reserved
for calculation of the subsequent bit level. The CAN
specification defines this time to be less than or equal
to 2 T
define this time to be 2 T
must be at least 2 T
Q
, it is possible to specify multiple sampling of the bus
Q
to 8 T
Q
. The PIC18F6585/8585/6680/8680 devices
Q
SYNCHRONIZATION SEGMENT
PROPAGATION SEGMENT
PHASE BUFFER SEGMENTS
SAMPLE POINT
INFORMATION PROCESSING TIME
by setting the PRSEG2:PRSEG0 bits.
Q
Q
.
long.
Q
Q
to 8 T
Q
, or it may be defined to be
. Thus, Phase Segment 2
Q
in duration. However,
DS30491C-page 337
Q
/2 between
Q
to 8 T
Q
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