PIC18LF6680-I/L Microchip Technology, PIC18LF6680-I/L Datasheet - Page 340
![IC, 8BIT MCU, PIC18LF, 40MHZ, PLCC-64](/photos/12/13/121323/c04-049_l_sml.jpg)
PIC18LF6680-I/L
Manufacturer Part Number
PIC18LF6680-I/L
Description
IC, 8BIT MCU, PIC18LF, 40MHZ, PLCC-64
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PCM18XK1.pdf
(496 pages)
3.PIC18F6585-IPT.pdf
(8 pages)
4.PIC18F6585-IPT.pdf
(38 pages)
5.PIC18F6585-IPT.pdf
(14 pages)
Specifications of PIC18LF6680-I/L
Controller Family/series
PIC18
No. Of I/o's
53
Eeprom Memory Size
1024Byte
Ram Memory Size
3328Byte
Cpu Speed
40MHz
No. Of Timers
4
Core Size
8 Bit
Program Memory Size
32768 Words
Core Processor
PIC
Speed
40MHz
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
52
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
3.25K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
68-PLCC
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3328 B
Interface Type
I2C, SPI, AUSART, CAN
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
53
Number Of Timers
8
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18LF6680-I/L
Manufacturer:
MICROCHIP
Quantity:
3 000
- PIC16F616T-ISL PDF datasheet
- PCM18XK1 PDF datasheet #2
- PIC18F6585-IPT PDF datasheet #3
- PIC18F6585-IPT PDF datasheet #4
- PIC18F6585-IPT PDF datasheet #5
- Current page: 340 of 496
- Download datasheet (9Mb)
PIC18F6585/8585/6680/8680
23.10 Synchronization
To compensate for phase shifts between the oscillator
frequencies of each of the nodes on the bus, each CAN
controller must be able to synchronize to the relevant
signal edge of the incoming signal. When an edge in
the transmitted data is detected, the logic will compare
the location of the edge to the expected time
(Sync_Seg). The circuit will then adjust the values of
Phase Segment 1 and Phase Segment 2 as necessary.
There are two mechanisms used for synchronization.
23.10.1
Hard synchronization is only done when there is a
recessive to dominant edge during a bus Idle condition,
indicating the start of a message. After hard synchroni-
zation, the bit time counters are restarted with
Sync_Seg. Hard synchronization forces the edge
which has occurred to lie within the synchronization
segment of the restarted bit time. Due to the rules of
synchronization, if a hard synchronization occurs there
will not be a resynchronization within that bit time.
23.10.2
As a result of resynchronization, Phase Segment 1
may be lengthened or Phase Segment 2 may be short-
ened. The amount of lengthening or shortening of the
phase buffer segments has an upper bound given by
the Synchronization Jump Width (SJW). The value of
the SJW will be added to Phase Segment 1 (see
Figure 23-5) or subtracted from Phase Segment 2 (see
Figure 23-6). The SJW is programmable between 1 T
and 4 T
Clocking information will only be derived from reces-
sive to dominant transitions. The property that only a
fixed maximum number of successive bits have the
same value, ensures resynchronization to the bit
stream during a frame.
DS30491C-page 338
Q
.
HARD SYNCHRONIZATION
RESYNCHRONIZATION
Q
The phase error of an edge is given by the position of
the edge relative to Sync_Seg, measured in T
phase error is defined in magnitude of T
• e = 0 if the edge lies within Sync_Seg.
• e > 0 if the edge lies before the sample point.
• e < 0 if the edge lies after the sample point of the
If the magnitude of the phase error is less than, or equal
to the programmed value of the synchronization jump
width, the effect of a resynchronization is the same as
that of a hard synchronization.
If the magnitude of the phase error is larger than the
synchronization jump width, and if the phase error is
positive, then Phase Segment 1 is lengthened by an
amount equal to the synchronization jump width.
If the magnitude of the phase error is larger than the
resynchronization jump width, and if the phase error is
negative, then Phase Segment 2 is shortened by an
amount equal to the synchronization jump width.
23.10.3
• Only one synchronization within one bit time is
• An edge will be used for synchronization only if
• All other recessive to dominant edges fulfilling
previous bit.
allowed.
the value detected at the previous sample point
(previously read bus value) differs from the bus
value immediately after the edge.
rules 1 and 2 will be used for resynchronization,
with the exception that a node transmitting a
dominant bit will not perform a resynchronization
as a result of a recessive to dominant edge with a
positive phase error.
SYNCHRONIZATION RULES
2004 Microchip Technology Inc.
Q
as follows:
Q
. The
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