STA339BWTR STMicroelectronics, STA339BWTR Datasheet - Page 44

• Manufacturer Part Number: STA339BWTR
• Description: DIG AUDIO SYSTEM, 2-CH, 36POWERSSOP
• Manufacturer: STMicroelectronics

Specifications of STA339BWTR

• Svhc: No SVHC (15-Dec-2010)
• No. Of Pins: 36
• Operating Temperature Range: -20°C To +70°C
• Supply Voltage Max: 26V
• Supply Voltage Min: 5V
• Termination T: RoHS Compliant
• Package / Case: PowerSSO
• Interface: I2C
• Interface Type: I2C
• Rohs Compliant: Yes

Register description
6.6.2
6.6.3
6.6.4
6.6.5
6.6.6
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Invalid input detect mute enable
Table 46.
Setting the IDE bit enables this function, which looks at the input I
mutes if the signals are perceived as invalid.
Binary output mode clock loss detection
Table 47.
Detects loss of input MCLK in binary mode and will output 50% duty cycle.
LRCK double trigger protection
Table 48.
Actively prevents double trigger of LRCLK.
Auto EAPD on clock loss
Table 49.
When active, issues a power device power down signal (EAPD) on clock loss detection.
IC power down
Table 50.
The PWDN register is used to place the IC in a low-power state. When PWDN is written
as 0, the output begins a soft-mute. After the mute condition is reached, EAPD is asserted
to power down the power-stage, then the master clock to all internal hardware expect the
I
2
2
3
4
5
7
C block is gated. This places the IC in a very low power consumption state.
Bit
Bit
Bit
Bit
Bit
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Invalid input detect mute enable
Binary output mode clock loss detection
LRCK double trigger protection
Auto EAPD on clock loss
IC power down
1
1
1
0
1
RST
RST
RST
RST
RST
IDE
BCLE
LDTE
ECLE
PWDN
Doc ID 15251 Rev 5
Name
Name
Name
Name
Name
Setting of 1 enables the automatic invalid input
detect mute
Binary output mode clock loss detection enable
LRCLK double trigger protection enable
Auto EAPD on clock loss
0: IC power down low-power condition
1: IC normal operation
Description
Description
Description
Description
Description
2
S data and automatically
STA339BW