STA339BWTR STMicroelectronics, STA339BWTR Datasheet
STA339BWTR
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STA339BWTR Summary of contents
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... Preset night-time listening mode Individual channel and master soft/hard mute Table 1. Device summary Order code STA339BW STA339BWTR August 2010 2.1-channel high-efficiency digital audio system Independent channel volume and DSP bypass Automatic zero-detect mute Automatic invalid input-detect mute 2-channel I ...
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Contents Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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STA339BW 5.4.4 5.4.5 5.4.6 6 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Contents 6.5.7 6.5.8 6.6 Configuration register F (addr 0x05 6.6.1 6.6.2 ...
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STA339BW 6.11.6 6.11.7 6.11.8 6.12 User-defined coefficient control registers (addr 0x16 - 0x26 6.12.1 6.12.2 6.12.3 6.12.4 6.12.5 6.12.6 6.12.7 6.12.8 6.12.9 6.12.10 Coefficient a1 data register bits 7:0 ...
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Contents 6.19 EQ soft volume configuration registers (addr 0x37 - 0x38 6.20 DRC RMS filter coefficients (addr 0x39 - 0x3E ...
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STA339BW List of figures Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of tables List of tables Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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STA339BW Table 49. Auto EAPD on clock loss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... FFX-power output stage, thereby creating a high-power single-chip FFX comprising high-quality, high-efficiency, all digital amplification. STA339BW is based on FFX (fully flexible amplification) processor, a STMicroelectronics proprietary technology. FFX is the evolution and the enlargement of the ST ternary technology: the new processor can be configured to work in ternary, binary, binary differential and phase shift PWM modulation schemes ...
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STA339BW 1.1 Block diagram Figure 1. Block diagram interface Volume control PLL Digital DSP Protection current/thermal Power control FFX Regulators Doc ID 15251 Rev 5 Channel 1A Channel 1B Logic Channel 2A Channel 2B ...
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Pin connections 2 Pin connections 2.1 Connection diagram Figure 2. Pin connection PowerSSO-36 (top view) GND_SUB TEST_MODE VCC_REG GND_REG OUT3B / FFX3B OUT3A / FFX3A 2.2 Pin description Table 2. Pin description Pin Type 1 GND ...
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STA339BW Table 2. Pin description (continued) Pin Type 11 Power 12 GND GND 15 Power I/O 21 Power 22 GND Power GND ...
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Electrical specifications 3 Electrical specifications 3.1 Absolute maximum ratings Table 3. Absolute maximum ratings Symbol V Power supply voltage (VCCxA, VCCxB) CC VDD_DIG Digital supply voltage VDD_PLL PLL supply voltage T Operating junction temperature op T Storage temperature stg Warning: ...
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STA339BW 3.3 Recommended operating conditions Table 5. Recommended operating condition Symbol V Power supply voltage (VCCxA, VCCxB) CC VDD_DIG Digital supply voltage VDD_PLL PLL supply voltage T Ambient temperature amb 3.4 Electrical specifications for the digital section Table 6. Electrical ...
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Electrical specifications 3.5 Electrical specifications for the power section The specifications given in this section are valid for the operating conditions kHz 384 kHz Table 7. Electrical specifications - power section Symbol ...
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STA339BW Table 7. Electrical specifications - power section (continued) Symbol Parameter THD+N Total harmonic distortion + noise X Crosstalk TALK Peak efficiency, FFX mode η Peak efficiency,binary modes 1. Refer to Figure 5: Test circuit 1. 2. Limit current if ...
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Electrical specifications 3.6 Power on/off sequence Figure 3. Power-on sequence VCC VCC VCC VCC VCC VDD_Dig VDD_Dig VDD_Dig VDD_Dig VDD_Dig XTI XTI XTI XTI XTI Reset Reset Reset Reset Reset ...
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STA339BW 3.7 Testing 3.7.1 Functional pin definition Table 8. Functional pin definition Pin name Number PWRDN 23 TWARN 20 EAPD 19 Figure 5. Test circuit 1 Duty cycle = 50% Figure 6. Test circuit 2 Duty cycle=A DTin(A) INxA Logic ...
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Processing data paths 4 Processing data paths The whole processing chain is composed of two consecutive sections. In the first one dual-channel processing is implemented, as described below. Then each channel is fed into the post-mixing block where there is ...
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STA339BW Figure 8. Processing part 2 Dual-band DRC enabled Dual-band DRC disabled Volume Volume C1Mx1 = C1Mx1 = C1Mx1 C1Mx1 0x7FFFFF 0x7FFFFF Hi-Pass Hi-Pass ...
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I C bus specification bus specification The STA339BW supports the I slave) and the output port SDA_OUT (slave to master). This protocol defines any device that sends data on to the bus as a transmitter ...
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STA339BW 5.3 Write operation Following the START condition the master sends a device select code with the RW bit set to 0. The STA339BW acknowledges this and the writes for the byte of internal address. After receiving the internal byte ...
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I C bus specification 5.4.5 Write mode sequence Figure 9. Write mode sequence BYTE WRITE START MULTIBYTE WRITE START 5.4.6 Read mode sequence Figure 10. Read mode sequence CURRENT DEV-ADDR ADDRESS READ START RANDOM DEV-ADDR ADDRESS READ START SEQUENTIAL ...
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STA339BW 6 Register description Table 9. Register summary Addr Name D7 0x00 CONFA FDRB 0x01 CONFB C2IM 0x02 CONFC OCRB 0x03 CONFD SME 0x04 CONFE SVE 0x05 CONFF EAPD 0x06 MUTE/LOC LOC1 0x07 MVOL MV7 0x08 C1VOL C1V7 0x09 C2VOL ...
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Register description Table 9. Register summary (continued) Addr Name D7 0x20 A2CF1 C4B23 0x21 A2CF2 C4B15 0x22 A2CF3 C4B7 0x23 B0CF1 C5B23 0x24 B0CF2 C5B15 0x25 B0CF3 C5B7 0x26 CFUD 0x27 MPCC1 MPCC15 0x28 MPCC2 MPCC7 0x29 DCC1 DCC15 0x2A ...
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STA339BW 6.1 Configuration register A (addr 0x00 FDRB TWAB 0 1 6.1.1 Master clock select Table 10. Master clock select Bit R/W 0 R/W 1 R/W 2 R/W The STA339BW supports sample rates of 32 kHz, 44.1 kHz, ...
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Register description 6.1.2 Interpolation ratio select Table 12. Internal interpolation ratio Bit R/W 4:3 R/W The STA339BW has variable interpolation (oversampling) settings such that internal processing and FFX output rates remain consistent. The first processing block interpolates by either 2-times ...
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STA339BW condition. When TWARN is asserted (set to 0) for a period of time greater than 400 ms, the power control block forces output limit (determined by TWOCL in the coefficient RAM) to the modulation limit in ...
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Register description 6.2.2 Serial data interface The STA339BW audio serial input was designed to interface with standard digital audio components and to accept a number of serial data formats. STA339BW always acts as slave when receiving audio input from standard ...
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STA339BW Table 20. Supported serial audio input formats for LSB-first (SAIFB = 1) BICKI make the STA339BW work properly, the serial audio interface LRCKI clock must be synchronous to the ...
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Register description happens. At the same time any processing related to the I only after the serial audio interface and the internal PLL are synchronous again. Note: Any mute or volume change causes some delay in the completion of the ...
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STA339BW 6.3 Configuration register C (addr 0x02 OCRB Reserved 1 0 6.3.1 FFX power output mode Table 23. FFX power output mode Bit R R/W 1 The FFX power output mode selects how the ...
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Register description 6.3.3 Overcurrent warning detect adjustment bypass Table 27. Overcurrent warning bypass Bit R/W 7 R/W 1 The OCWARN input is used to indicate an overcurrent warning condition. When OCWARN is asserted (set to 0), the power control block ...
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STA339BW 6.4.4 Post-scale link Table 31. Post-scale link Bit R/W 3 R/W 0 Post-scale functionality can be used for power-supply error correction. For multi-channel applications running off the same power-supply, the post-scale values can be linked to the value of ...
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Register description 6.4.8 Submix mode enable Table 35. Submix mode enable Bit R/W 7 R/W 0 6.5 Configuration register E (addr 0x04 SVE ZCE 1 1 6.5.1 Max power correction variable Table 36. Max power correction variable Bit ...
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STA339BW 6.5.4 AM mode enable Table 39. AM mode enable Bit R/W RST 3 R/W 0 STA339BW features aFFX processing mode that minimizes the amount of noise generated in frequency range of AM radio. This mode is intended for use ...
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Register description 6.6 Configuration register F (addr 0x05 EAPD PWDN 0 1 6.6.1 Output configuration Table 44. Output configuration Bit R R/W 0 Table 45. Output configuration engine selection OCFG[1:0] 2 channel (full-bridge) power, ...
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STA339BW Figure 11. OCFG = 00 (default value) Figure 12. OCFG = 01 Figure 13. OCFG = 10 OUT1A Half Bridge Channel 1 Half Bridge OUT1B OUT2A Half Bridge Channel 2 Half Bridge OUT2B OUT3A LineOut 1 LPF OUT3B OUT4A ...
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Register description Figure 14. OCFG = 11 The STA339BW can be configured to support different output configurations. For each PWM output channel a PWM slot is defined. A PWM slot is always fs) seconds length. The ...
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STA339BW 2.0 channels, two full bridges (OCFG = 00) FFX1A -> OUT1A FFX1B -> OUT1B FFX2A -> OUT2A FFX2B -> OUT2B FFX3A -> OUT3A FFX3B -> OUT3B FFX4A -> OUT4A FFX4B -> OUT4B FFX1A/1B configured as ternary FFX2A/2B configured as ...
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Register description 2.1 channels, two half bridges + one full bridge (OCFG = 01) FFX1A -> OUT1A FFX2A -> OUT1B FFX3A -> OUT2A FFX3B -> OUT2B FFX1A -> OUT3A FFX1B -> OUT3B FFX2A -> OUT4A FFX2B -> OUT4B FFX1A/1B configured ...
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STA339BW 2.1 channels, two fullbridge + one external full bridge (OCFG = 10) FFX1A -> OUT1A FFX1B -> OUT1B FFX2A -> OUT2A FFX2B -> OUT2B FFX3A -> OUT3A FFX3B -> OUT3B EAPD -> OUT4A TWARN -> OUT4B FFX1A/1B configured as ...
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Register description 6.6.2 Invalid input detect mute enable Table 46. Invalid input detect mute enable Bit R/W 2 R/W 1 Setting the IDE bit enables this function, which looks at the input I mutes if the signals are perceived as ...
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STA339BW 6.6.7 External amplifier power down Table 51. External amplifier power down Bit R/W 7 R/W 0 The EAPD register directly disables/enables the internal power circuitry. When EAPD = 0, the internal power section is placed on a low-power state ...
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Register description 6.7.5 Channel 3 / line output volume D7 D6 C3V7 C3V6 0 1 The Volume structure of the STA339BW consists of individual volume registers for each channel and a master volume register that provides an offset to each ...
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STA339BW Table 54. Channel volume as a function of CxV[7:0] (continued) CxV[7:0] 01100001 (0x61) … 11010111 (0xD7) 11011000 (0xD8) 11011001 (0xD9) 11011010 (0xDA) … 11101100 (0xEC) 11101101 (0xED) … 11111111 (0xFF) 6.8 Audio preset registers (addr 0x0B and 0x0C) 6.8.1 ...
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Register description 6.8.3 AM interference frequency switching Table 56. AM interference frequency switching bits Bit R/W 0 R/W 0 Table 57. Audio preset AM switching frequency selection AMAM[2:0] 000 001 010 011 100 101 110 6.8.4 Bass management crossover Table ...
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STA339BW Table 59. Bass management crossover frequency (continued) XO[3:0] 1010 1011 1100 1101 1110 1111 6.9 Channel configuration registers (addr 0x0E - 0x10 C1OM1 C1OM0 C2OM1 C2OM0 C3OM1 C3OM0 1 ...
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Register description 6.9.3 Volume bypass Each channel contains an individual channel volume bypass particular channel has volume bypassed via the CxVBP = 1 register then only the channel volume setting for that particular channel affects the volume setting, ...
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STA339BW 6.10 Tone control register (addr 0x11 TTC3 TTC2 0 1 6.10.1 Tone control Table 65. Tone control boost/cut as a function of BTC and TTC bits BTC[3:0]/TTC[3:0] 0000 0001 … 0111 0110 0111 1000 1001 … 1101 ...
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Register description 6.11.4 Limiter 2 attack/release threshold D7 D6 L2AT3 L2AT2 0 1 The STA339BW includes two independent limiter blocks. The purpose of the limiters is to automatically reduce the dynamic range of a recording to prevent the outputs from ...
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STA339BW Figure 19. Basic limiter and volume flow diagram Table 66. Limiter attack rate as a function of LxA bits LxA[3:0] Attack Rate dB/ms 0000 3.1584 0001 2.7072 0010 2.2560 0011 1.8048 0100 1.3536 0101 0.9024 0110 0.4512 0111 0.2256 ...
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Register description Anti-clipping mode Table 68. Limiter attack threshold as a function of LxAT bits (AC mode) LxAT[3:0] AC (dB relative to fs) 0000 -12 0001 -10 0010 -8 0011 -6 0100 -4 0101 -2 0110 0 0111 +2 1000 ...
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STA339BW Dynamic range compression mode Table 70. Limiter attack threshold as a function of LxAT bits (DRC mode) LxAT[3:0] DRC (dB relative to Volume) 0000 -31 0001 -29 0010 -27 0011 -25 0100 -23 0101 -21 0110 -19 0111 -17 ...
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Register description 6.11.7 Limiter 2 Extended attack threshold (addr 0x34 EATHEN2 EATH2[6] TBD TBD The extended attack threshold value is determined as follows: attack threshold = -12 + EATH2 / 4 6.11.8 Limiter 2 Extended release threshold (addr ...
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STA339BW 6.12.5 Coefficient b2 data register bits 23: C2B23 C2B22 0 0 6.12.6 Coefficient b2 data register bits 15 C2B15 C2B14 0 0 6.12.7 Coefficient b2 data register bits 7 C2B7 C2B6 0 0 ...
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Register description 6.12.12 Coefficient a2 data register bits 15 C4B15 C4B14 0 0 6.12.13 Coefficient a2 data register bits 7 C4B7 C4B6 0 0 6.12.14 Coefficient b0 data register bits 23: C5B23 C5B22 0 ...
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STA339BW For example, in case of different input sources (different sampling rates), the three different sets of coefficients can be downloaded once at the start up, and during the normal play it is possible to switch among the three RAM ...
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Register description Writing a single coefficient to RAM 1. Select the RAM block with register 0x31 bit1, bit0. 2. Write 6 bits of address Write top 8 bits of coefficient Write middle 8 bits ...
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STA339BW 6.12.18 User-defined EQ The STA339BW can be programmed for four EQ filters (biquads) per each of the two input channels. The biquads use the following equation ...
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Register description 6.12.21 Overcurrent postscale The STA339BW provides a simple mechanism for reacting to overcurrent detection in the power block. When the ocwarn input is asserted, the overcurrent postscale value is used in place of the normal postscale value to ...
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STA339BW Table 72. RAM block for biquads, mixing, scaling and bass management (continued) Index (decimal) Index (hex) 54 0x36 55 0x37 56 0x38 57 0x39 58 0x3A 59 0x3B 60 0x3C 61 0x3D 62 0x3E 63 0x3F 6.13 Variable max ...
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Register description 6.15 Fault detect recovery constant registers (addr 0x2B - 0x2C FDRC15 FDRC14 FDRC7 FDRC6 0 0 FDRC bits specify the 16-bit fault detect recovery time delay. When FAULT is asserted, the TRISTATE ...
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STA339BW 6.17 EQ coefficients and DRC configuration register (addr 0x31 XOB 0 0 Table 74. EQ RAM select SEL[1:0] 00/ Bits AMGC[3:2] change the behavior of the bits AMGC[1:0] as given in Table 75. Anti-clipping and ...
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Register description 6.18.1 Dual-band DRC The STA339BW provides a dual-band DRC (B path, as depicted in 2 Figure 20. B DRC scheme The low-frequency information (LFE) is extracted from the left and ...
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STA339BW A first-order filter is suggested to guarantee that for every ω filter obtained as difference (as shown in filter) frequency response, and the corresponding recombination after the DRC has low ripple. Second-order filters can be used as well, but ...
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Register description 6.18.3 Extended post scale range Table 77. Post scale setup PS48DB 0 1 Post scale is an attenuation by default. When PS48DB is set 48-dB offset is applied to the configured word, so postscale can ...
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STA339BW 6.18.5 Extended BIQUAD selector De-ephasis filter as well as bass and treble controls can be configured as user defined filters when equalization coefficients link is activated (BQL = 1) and the corresponding BQx bit is set to 1. Table ...
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Register description Table 83. Soft volume (increasing) setup SVUPE 0 1 When SVUPE = 1 the fade-in rate is defined by the SVUP[4:0] bits according to the formula: Fade-in rate = 48 / (SVUP[4: dB/ms. Table 84. Soft ...
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STA339BW 7 Application 7.1 Application scheme for power supplies Here in Figure 22 supply decoupling. Particular care has to be taken with the layout of the PCB. In particular the 3.3 Ω resistors on the digital supplies (VDD_DIG) have to ...
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Application 7.3 Typical output configuration Here after the typical output configuration used for BTL stereo mode. Please refer to the application note for all the other possible output configuration recommended schematics. Figure 23. Output configuration for stereo BTL mode OUT1A ...
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STA339BW 8 Package thermal characteristics Using a double-layer PCB the thermal resistance junction to ambient with 2 copper ground areas The dissipated power within the device depends primarily on the supply voltage, load impedance and ...
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Package mechanical data 9 Package mechanical data Figure 26 shows the package outline and PowerSSO-36 package with exposed pad (slug) down (EPD). Table 85. PowerSSO-36 EPD dimensions Symbol Min A 2. 0.18 c 0.23 D ...
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Figure 26. PowerSSO-36 EPD outline drawing h x 45° ...
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Revision history 10 Revision history Table 86. Document revision history Date 09-Dec-2008 16-Feb-2009 01-Apr-2009 15-May-2009 04-Aug-2010 76/77 Revision 1 Initial release Updated names/descriptions for pins 17-20 in Added cross reference to I on/off sequence on page 18 2 Updated text ...
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... STA339BW Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...