DSPIC33FJ128GP802-E/MM Microchip Technology, DSPIC33FJ128GP802-E/MM Datasheet - Page 84

• Manufacturer Part Number: DSPIC33FJ128GP802-E/MM
• Description: IC, DSC, 16BIT, 128KB 40MHZ, 3.6V, QFN28
• Manufacturer: Microchip Technology
• Series: DsPIC33Fr

Specifications of DSPIC33FJ128GP802-E/MM

• Core Frequency: 40MHz
• Core Supply Voltage: 3.6V
• No. Of I/o's: 21
• Flash Memory Size: 128KB
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -40°C To +125°C
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: CAN, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: AC'97, Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b/12b, D/A 4x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-QFN
• Rohs Compliant: Yes
• Package: 28QFN-S EP
• Device Core: dsPIC
• Family Name: dSPIC33
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 21
• Interface Type: CAN/I2C/SPI/UART
• On-chip Adc: 10-chx10-bit|10-chx12-bit
• On-chip Dac: 2-chx16-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
TABLE 6-2:
6.2
A Power-on Reset (POR) circuit ensures the device is
reset from power-on. The POR circuit is active until
V
has elapsed. The delay T
device bias circuits become stable.
The device supply voltage characteristics must meet
the
requirements
Section 30.0 “Electrical Characteristics” for details.
The POR status (POR) bit in the Reset Control
(RCON<0>) register is set to indicate the Power-on
Reset.
DS70292D-page 84
V
T
V
T
T
T
DD
POR
BOR
PWRT
FSCM
POR
BOR
Note:
crosses the V
specified
Power-on Reset (POR)
When the device exits the Reset condi-
tion (begins normal operation), the
device operating parameters (voltage,
frequency, temperature, etc.) must be
within their operating ranges, otherwise
the device may not function correctly.
The user application must ensure that
the delay between the time power is
first applied, and the time SYSRST
becomes inactive, is long enough to get
all
specification.
Symbol
to
starting
OSCILLATOR DELAY
operating
POR
generate the POR. Refer to
threshold and the delay T
voltage
POR
parameters
ensures the internal
POR threshold
POR extension time
BOR threshold
BOR extension time
Programmable power-up time delay
Fail-Safe Clock Monitor Delay
and
rise
within
POR
rate
Parameter
Preliminary
6.2.1
The on-chip regulator has a Brown-out Reset (BOR)
circuit that resets the device when the V
(V
cuit keeps the device in Reset until V
threshold and the delay T
T
stable.
The BOR status (BOR) bit in the Reset Control
(RCON<1>) register is set to indicate the Brown-out
Reset.
The device will not run at full speed after a BOR as the
V
operation. The PWRT provides power-up time delay
(T
stabilized at the appropriate levels for full-speed
operation before the SYSRST is released.
The power-up timer delay (T
the
(FPWRT<2:0>)
(FPOR<2:0>) register, which provides eight settings
(from 0 ms to 128 ms). Refer to Section 27.0 “Special
Features” for further details.
Figure 6-3 shows the typical brown-out scenarios. The
reset delay (T
rises above the V
BOR
DD
PWRT
DD
< V
should rise to acceptable levels for full-speed
ensures the voltage regulator output becomes
Power-on
) to ensure that the system power supplies have
BOR
Brown-out Reset (BOR) and
Power-up timer (PWRT)
) for proper device operation. The BOR cir-
1.8V nominal
30 s maximum
2.5V nominal
100 s maximum
0-128 ms nominal
900 s maximum
BOR
BOR
bits
+ T
Reset
PWRT
trip point
in
 2009 Microchip Technology Inc.
BOR
) is initiated each time V
the
PWRT
Timer
has elapsed. The delay
Value
POR
) is programmed by
DD
Value
crosses V
Configuration
DD
is too low
Select
BOR
DD