DSPIC33FJ128GP802-E/MM Microchip Technology, DSPIC33FJ128GP802-E/MM Datasheet - Page 266

• Manufacturer Part Number: DSPIC33FJ128GP802-E/MM
• Description: IC, DSC, 16BIT, 128KB 40MHZ, 3.6V, QFN28
• Manufacturer: Microchip Technology
• Series: DsPIC33Fr

Specifications of DSPIC33FJ128GP802-E/MM

• Core Frequency: 40MHz
• Core Supply Voltage: 3.6V
• No. Of I/o's: 21
• Flash Memory Size: 128KB
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -40°C To +125°C
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: CAN, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: AC'97, Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b/12b, D/A 4x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-QFN
• Rohs Compliant: Yes
• Package: 28QFN-S EP
• Device Core: dsPIC
• Family Name: dSPIC33
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 21
• Interface Type: CAN/I2C/SPI/UART
• On-chip Adc: 10-chx10-bit|10-chx12-bit
• On-chip Dac: 2-chx16-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
22.4
The DAC clock signal clocks the internal logic of the
Audio DAC module. The data sample rate of the Audio
DAC is an integer division of the rate of the DAC clock.
The DAC clock is generated via a clock divider circuit
that accepts an auxiliary clock from the auxiliary
oscillator.
FIGURE 22-1:
FIGURE 22-2:
DS70292D-page 266
DAC Clock
CONTROL
Note: V
Note 1:
Count (DAC1RDAT)
Output (DAC1RN)
Output (DAC1RP)
OD
Negative DAC
Positive DAC
DAC input
+ = V
BLOCK DIAGRAM OF AUDIO DIGITAL-TO-ANALOG (DAC) CONVERTER
AUDIO DAC OUTPUT FOR RAMP INPUT (UNSIGNED)
If DAC1RDAT and DAC1LDAT are empty, data will be taken from the DACDFLT register.
DACH
V
0x0000
0xFFFF
V
V
DACFDIV<6:0>
V
DACL
DACL
DACH
DACH
– V
DACL
V
V
DACM
ACLK
DACM
, V
OD
DAC1RDAT
DAC1LDAT
- = V
CLK DIV
DACL
– V
Preliminary
DACH
; refer to Audio DAC Module Specifications, Table 30-42, for typical values.
DACDFLT
The divisor ratio is programmed by clock divider bits
(DACFDIV<6:0>)
(DAC1CON). The resulting DAC clock must not exceed
25.6 MHz. If lower sample rates are to be used, then
the DAC filter clock frequency may be reduced to
reduce power consumption. The DAC clock frequency
is 256 times the sampling frequency.
Note 1
Note 1
D/A
D/A
in
 2009 Microchip Technology Inc.
the
Amp
Amp
DAC
Right Channel
Control
Left Channel
DAC1RM
DAC1RP
DAC1RN
DAC1LM
DAC1LP
DAC1LN
register