DSPIC33FJ128GP802-E/MM Microchip Technology, DSPIC33FJ128GP802-E/MM Datasheet - Page 83

• Manufacturer Part Number: DSPIC33FJ128GP802-E/MM
• Description: IC, DSC, 16BIT, 128KB 40MHZ, 3.6V, QFN28
• Manufacturer: Microchip Technology
• Series: DsPIC33Fr

Specifications of DSPIC33FJ128GP802-E/MM

• Core Frequency: 40MHz
• Core Supply Voltage: 3.6V
• No. Of I/o's: 21
• Flash Memory Size: 128KB
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -40°C To +125°C
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: CAN, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: AC'97, Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b/12b, D/A 4x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-QFN
• Rohs Compliant: Yes
• Package: 28QFN-S EP
• Device Core: dsPIC
• Family Name: dSPIC33
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 21
• Interface Type: CAN/I2C/SPI/UART
• On-chip Adc: 10-chx10-bit|10-chx12-bit
• On-chip Dac: 2-chx16-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

FIGURE 6-2:
 2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
Oscillator Clock
Device Status
POR Reset
BOR Reset
Note 1: POR Reset: A POR circuit holds the device in Reset when the power supply is turned on. The POR circuit is
SYSRST
FSCM
V
DD
2: BOR Reset: The on-chip voltage regulator has a BOR circuit that keeps the device in Reset until V
3: PWRT Timer: The programmable power-up timer continues to hold the processor in Reset for a specific
4: Oscillator Delay: The total delay for the clock to be ready for various clock source selections are given in
5: When the oscillator clock is ready, the processor begins execution from location 0x000000. The user
6: The Fail-safe clock monitor (FSCM), if enabled, begins to monitor the system clock when the system clock is
active until V
the V
becomes stable.
period of time (T
at the appropriate level for full-speed operation. After the delay T
inactive, which in turn enables the selected oscillator to start generating clock cycles.
Table 6-1. Refer to Section 9.0 “Oscillator Configuration” for more information.
application programs a GOTO instruction at the reset address, which redirects program execution to the
appropriate start-up routine.
ready and the delay T
1
SYSTEM RESET TIMING
BOR
2
threshold and the delay T
DD
T
crosses the V
PWRT
V
POR
POR
) after a BOR. The delay T
FSCM
elapsed.
POR
threshold and the delay T
Preliminary
Vbor
V
BOR
BOR
has elapsed. The delay T
T
PWRT
T
3
BOR
Reset
Time
PWRT
ensures that the system power supplies have stabilized
T
OSCD
POR
has elapsed.
PWRT
BOR
T
OST
4
ensures the voltage regulator output
has elapsed, the SYSRST becomes
T
LOCK
DS70292D-page 83
5
6
Run
DD
T
FSCM
crosses