SC28L92A1A NXP Semiconductors, SC28L92A1A Datasheet - Page 58
SC28L92A1A
Manufacturer Part Number
SC28L92A1A
Description
UART, DUAL, 3.3V OR 5V, SMD, 28L92
Manufacturer
NXP Semiconductors
Datasheet
1.SC28L92A1B557.pdf
(73 pages)
Specifications of SC28L92A1A
No. Of Channels
2
Supply Voltage Range
2.97V To 3.63V, 4.5V To 5.5V
Operating Temperature Range
-40°C To +85°C
Digital Ic Case Style
PLCC
No. Of Pins
44
Svhc
No SVHC (18-Jun-2010)
Operating
RoHS Compliant
Data Rate
230.4Kilobaud
Uart Features
Programmable Channel Mode, Line Break Detection & Generation
Rohs Compliant
Yes
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NXP Semiconductors
[7]
11. Timing diagrams
SC28L92_7
Product data sheet
Minimum DACKN time is ((t
cycles, the 80xxx bus timing may be used while in the 68xxx mode. It is not necessary to wait for DACKN to insure the proper operation
of the SC26C92. In all cases the data will be written to the SC28L92 on the falling edge of DACKN or the rise of CEN. The fall of CEN
initializes the bus cycle. The rise of CEN ends the bus cycle. DACKN LOW or CEN HIGH completes the write cycle.
Fig 10. Reset timing
Fig 11. Bus timing (80xxx mode)
DCR
RESET
a. 80xxx mode
or t
D0 to D7
D0 to D7
A0 to A3
DCW
(write)
(read)
WDN
RDN
CEN
) t
CSC
+ 2 X1 edges + rise time over 5 ns). Two X1 edges is 273 ns at 3.6864 MHz. For faster bus
float
Rev. 07 — 19 December 2007
3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
t
t
AS
CS
t
RES
not valid
t
AH
001aae303
t
DD
t
RW
t
DS
valid
valid
RESETN
b. 68xxx mode
t
CS
t
DF
t
DH
t
t
RWD
RWD
float
t
RES
SC28L92
© NXP B.V. 2007. All rights reserved.
001aae305
001aae304
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