MPC8572EAMC Freescale Semiconductor, MPC8572EAMC Datasheet - Page 42

• Manufacturer Part Number: MPC8572EAMC
• Description: MPC8572 AMC RAPID SYSTEM
• Manufacturer: Freescale Semiconductor
• Type: MPUr

Specifications of MPC8572EAMC

• Contents: Board
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: MPC8572E

MPC8572EAMC Functional Description
Therefore, front panel eTSEC1 Gigabit Ethernet has physical address 0x00h and eTSEC2/3/4 have
addresses 0x01h, 0x03h, and 0x04h, respectively. eTSEC1 and eTSEC2 are configured as SGMII copper
interfaces, and eTSEC3 and eTSEC4 are both configured as an SGMII fiber interface.
The last Ethernet interface used on the MPC8572EAMC is generated using Marvell’s 88E3018 PHY.
Using hardware configuration pins, this 10/100BaseT PHY is configured in much the same way as the
88E1112 PHYs that have just been discussed. The 88E3018 is configured using four configuration bits and
a three bit control word as shown in
The 88E3018 PHY uses the VSS, LED[0:2], CRS, COL and VDDO pins to drive different hardware
configuration words onto pins during power up.
88E3018’s configuration pins.
5-18
Config_4
Config_5
Config
Configuration
Table 5-10. 88E1112 Reset Configuration Settings (continued)
0 0
1 1
MPC8572EAMC Advanced Mezzanine Card User Guide, Rev. 1.2
Config0
Config1
Config2
Config3
Table 5-11. 88E3018 PHY Configuration Pins
Pin
Table 5-12. 8E3018 Pin Configuration Values
No EEPROM Read
SGMII MAC interface to 1000Base-X, auto media select, such as AdvancedMC
BACKPLANE
Table
MODE[2]
5-11.
Bit[2]
RES
RES
RES
LED[0]
LED[1]
LED[2]
VDDO
VSS
CRS
COL
Pin
Table 5-12
Bits[2:0]
PHYADDR[1]
PHYADDR[3]
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 1 0
1 1 1
MODE[1]
ENA_XC
Bit[1]
details the pins used to set the values of the
Comments
PHYADDR[0]
PHYADDR[2]
PHYADDR[4]
MODE[0]
Bit[0]
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