ISL6267HRZ Intersil, ISL6267HRZ Datasheet - Page 25

• Manufacturer Part Number: ISL6267HRZ
• Description: IC PWM CTRLR MULTIPHASE 48TQFN
• Manufacturer: Intersil

Specifications of ISL6267HRZ

• Applications: Converter, AMD Fusion™ CPU GPU
• Voltage - Input: 4.75 V ~ 5.25 V
• Number Of Outputs: 2
• Voltage - Output: 0.0125 V ~ 1.55 V
• Operating Temperature: -10°C ~ 100°C
• Mounting Type: *
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

For example, given N = 3, R
R
Equation 23 gives C
Assuming the compensator design is correct, Figure 21 shows the
expected load transient response waveforms if C
selected. When the load current I
output voltage V
If C
represent real-time I
Figure 22 shows the load transient response when C
small. V
a system failure. Figure 23 shows the transient response when
C
There is excessive overshoot if load insertion occurs during this
time, which may negatively affect the CPU reliability.
C
n
n
ntcs
is too large. V
n
FIGURE 21. DESIRED LOAD TRANSIENT RESPONSE
FIGURE 22. LOAD TRANSIENT RESPONSE WHEN C
FIGURE 23. LOAD TRANSIENT RESPONSE WHEN C
=
value is too large or too small, V
----------------------------------------------------------- -
R
---------------------------------------- -
R
= 2.61kΩ, R
ntcnet
ntcnet
core
sags excessively upon load insertion and may create
×
+
R
------------- -
R
------------- -
WAVEFORMS
SMALL
LARGE
L
core
sum
sum
core
N
N
ntc
n
also has a square response.
o
×
is sluggish in drooping to its final value.
= 10kΩ, DCR = 0.88mΩ and L = 0.36µH,
= 0.406µF.
(s) and worsens the transient response.
DCR
sum
25
= 3.65kΩ, R
o i
o i
V o
V o
o i
V o
core
has a square change, the
Cn
(s) does not accurately
p
= 11kΩ,
n
is correctly
n
n
n
IS TOO
IS TOO
is too
(EQ. 23)
ISL6267
Figure 24 shows the output voltage ring-back problem during
load transient response. The load current i
change, but the inductor current i
Instead, i
nature of the current loop. The ESR and ESL effect of the output
capacitors makes the output voltage V
current change. However, the controller regulates V
the droop current i
therefore, it pulls V
ring-back problem. This phenomenon is not observed when the
output capacitor has very low ESR and ESL, as is the case with all
ceramic capacitors.
Figure 25 shows two optional circuits for reduction of the
ring-back. C
constant. It usually takes the parallel of two (or more) capacitors
to get the desired value. Figure 25 shows that two capacitors
(C
component to reduce the V
C
change, the effective capacitance is less because R
the impedance of the C
to dip when C
ring-back. This effect is more pronounced when C
larger than C
However, the presence of R
if C
2200pF. R
n.2
n.1
n.2
FIGURE 25. OPTIONAL CIRCUITS FOR RING-BACK REDUCTION
provides the desired C
and C
is too small. It is recommended to keep C
FIGURE 24. OUTPUT VOLTAGE RING-BACK PROBLEM
Rntcs
Rntc
L
n
responds in first-order system fashion due to the
n.2
n
value usually is a few ohms. C
n.2
is the capacitor used to match the inductor time
n
) are in parallel. Resistor R
is too small, and this effect reduces the V
. It is also more pronounced when R
BACK
RING
Rp
droop
o
back to the level dictated by i
o i
n.1
OPTIONAL
, which is a real-time representation of i
branch. As Figure 22 shows, V
o
n
L i
n
Cn.1
ring-back. At steady state, C
capacitance. At the beginning of i
increases the ripple of the V
Rn
L
cannot accurately follow.
V o
o
OPTIONAL
dip quickly upon load
n
Rip
Cn.2
n.1
o
is an optional
Ri
has a fast step
, C
Cip
Vcn
n.2
n.2
n.1
L
ISUM+
ISUM-
o
and R
, causing the
January 31, 2011
n
n
greater than
according to
is much
increases
is bigger.
n
n.1
o
n
o
FN7801.0
values
signal
tends
+
o
L
;