ISL6267HRZ Intersil, ISL6267HRZ Datasheet - Page 16

• Manufacturer Part Number: ISL6267HRZ
• Description: IC PWM CTRLR MULTIPHASE 48TQFN
• Manufacturer: Intersil

Specifications of ISL6267HRZ

• Applications: Converter, AMD Fusion™ CPU GPU
• Voltage - Input: 4.75 V ~ 5.25 V
• Number Of Outputs: 2
• Voltage - Output: 0.0125 V ~ 1.55 V
• Operating Temperature: -10°C ~ 100°C
• Mounting Type: *
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Power-On Reset
Before the controller has sufficient bias to guarantee proper
operation, the ISL6267 requires both a +5V input supply tied to
V
V
thresholds. Once these thresholds are reached or exceeded, the
ISL6267 has enough bias to begin checking SVI inputs.
CC
IN
, to exceed their respective rising power-on reset (POR)
and PV
Interval 1 to 2: ISL6267 waits to POR.
Interval 2 to 3: SVC and SVD are externally set to pre-Metal VID code.
Interval 3 to 4: ENABLE locks pre-Metal VID code. All outputs soft-start to this level.
Interval 4 to 5: PGOOD signal goes HIGH, indicating proper operation.
Interval 5 to 6: CPU detects PGOOD high, and drives PWROK high, to allow ISL6267 to prepare for SVI commands.
Interval 6 to 7: SVC and SVD data lines communicate change in VID code.
Interval 7 to 8: ISL6267 responds to VID-ON-THE-FLY code change.
Interval 8 to 9: PWROK is driven low, and ISL6267 returns all outputs to pre-PWROK Metal VID level.
Interval 9 to 10: PWROK driven high once again by CPU, and ISL6267 prepares for SVI commands.
Interval 10 to 11: SVC and SVD data lines communicate new VID code.
Interval 11 to 12: ISL6267 drives outputs to new VID code level.
Post 12: Enable falls, all internal drivers are tri-stated, and PGOOD is driven low.
V
CORE
ENABLE
PWROK
PGOOD
FIGURE 12. TYPICAL SOFT-START WAVEFORMS
ENABLE
PWROK
PGOOD
/ V
CC
VCC
SVC
SVD
DAC
VDD
VIN
NB
, as well as a battery or other input supply tied to
800µs
FIGURE 13. SVI INTERFACE TIMING DIAGRAM: TYPICAL PRE-PWROK METAL VID START-UP
1.875mV/µs
1
16
SLEW RATE
MetalVID
2
3
VID COMMAND
VOLTAGE
METAL_VID
4
ISL6267
5
6
Hysteresis between the rising and the falling thresholds assure
the ISL6267 does not inadvertently turn off unless the bias
voltage drops substantially (see “Electrical Specifications” on
page 11).
Serial VID Interface
The on-board Serial VID Interface (SVI) circuitry allows the
processor to directly control the Core and Northbridge voltage
reference levels within the ISL6267. The SVC and SVD states are
decoded according to the PWROK inputs as described in the
following sections. The ISL6267 uses a digital-to-analog
converter (DAC) to generate a reference voltage based on the
decoded SVI value. See Figure 13 for a simple SVI interface
timing diagram.
Pre-PWROK Metal VID
Typical motherboard start-up begins with the controller decoding
the SVC and SVD inputs to determine the pre-PWROK Metal VID
setting (see Table 1). Once the ENABLE input exceeds the rising
threshold, the ISL6267 decodes and locks the decoded value in
an on-board hold register.
7
V_SVI
8
METAL_VID
9
10
11
V_SVI
12
January 31, 2011
FN7801.0