MC56F8255VLD Freescale Semiconductor, MC56F8255VLD Datasheet - Page 7

• Manufacturer Part Number: MC56F8255VLD
• Description: DSC 64K FLASH 60MHZ 44-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8255VLD

• Core Processor: 56800E
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 44-LQFP
• Product: DSCs
• Processor Series: 56800E
• Core: 56800E
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 35
• Data Ram Size: 8 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 4 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

2.4.2
2.4.3
The masking of interrupt priority level is managed by the 56800E core.
2.4.4
Freescale Semiconductor
•
•
•
•
•
•
•
•
•
•
•
•
Dual Harvard architecture that permits as many as three simultaneous accesses to program and data
memory
48 KB (24K  16) to 64 KB (32K  16) on-chip flash memory with 2048 bytes (1024  16) page
size
6 KB (3K  16) to 8 KB (4K  16) on-chip RAM that is byte-addressable
EEPROM emulation capability using flash
Support for 60 MHz program execution from both internal flash and RAM memories
Flash security and protection that prevent unauthorized users from gaining access to the internal
flash
Five interrupt priority levels
— Three user-programmable priority levels for each interrupt source:
— Unmaskable level 3 interrupts include:
— Maskable level 3 interrupts include:
— Lowest-priority software interrupt: level LP
Nested interrupts: higher priority level interrupt request can interrupt lower priority interrupt
subroutine
Two programmable fast interrupts that can be assigned to any interrupt source
Notification to system integration module (SIM) to restart clock out of wait and stop states
Ability to relocate interrupt vector table
Low-speed run, wait, and stop modes: as low as 781 Hz clock provided by OCCS and internal
ROSC
– Level 0
– Level 1
– Level 2
– Illegal instruction
– Hardware stack overflow
– Misaligned data access
– SWI3 instruction
– EOnCE step counter
– EOnCE breakpoint unit
– EOnCE trace buffer
Memory
Interrupt controller
Power-saving features
MC56F825x/MC56F824x Product Brief, Rev. 2
Preliminary
Features
7