DS90UR905QSQ/NOPB National Semiconductor, DS90UR905QSQ/NOPB Datasheet - Page 8

• Manufacturer Part Number: DS90UR905QSQ/NOPB
• Description: IC SER/DESERIAL 24BIT 48LLP
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of DS90UR905QSQ/NOPB

• Function: Serializer
• Data Rate: 1.82Gbps
• Input Type: Parallel
• Output Type: Serial
• Number Of Inputs: 24
• Number Of Outputs: 1
• Voltage - Supply: 1.71 V ~ 1.89 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 48-WFQFN, Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

www.national.com
Pin Name
OS_PCLK
OS_DATA
OP_LOW
OSS_SEL
RFB
EQ[3:0]
OSC_SEL[2:0]
SSC[3:0]
MAP_SEL[1:0]
Control and Configuration
PDB
ID[x]
SCL
SDA
BISTEN
RES
42 PASS
20 [G7],
21 [G6],
22 [G5],
26 [G2],
27 [G1],
34 [R6],
35 [R5],
36 [R4],
40 [R1],
23 [G4]
28 [G0]
37 R[3]
41 [R0]
11 [B5]
14 [B3]
17 [B2]
18 [B1]
Pin #
59
56
44
47
3
2
w/ pull-down
w/ pull-down
w/ pull-down
w/ pull-down
w/ pull-down
w/ pull-down
w/ pull-down
w/ pull-down
w/ pull-down
w/ pull-down
w/ pull-down
w/ pull-down
I, LVCMOS
I, LVCMOS
I, LVCMOS
I, LVCMOS
I, LVCMOS
I, LVCMOS
I, LVCMOS
I, LVCMOS
I, LVCMOS
I, LVCMOS
I, LVCMOS Serial Control Bus Clock Input - Optional
Open Drain
I, LVCMOS
I, LVCMOS
I/O, Type
LVCMOS
I, Analog
STRAP
STRAP
STRAP
STRAP
STRAP
STRAP
STRAP
STRAP
STRAP
I/O,
Description
PCLK Output Slew Select — Pin or Register Control
OS_PCLK = 1, increased PCLK slew
OS_PCLK = 0, normal (default)
Data Output Slew Select — Pin or Register Control
OS_DATA = 1, increased DATA slew
OS_DATA = 0, normal (default)
Outputs held Low when LOCK = 1 — Pin or Register Control
NOTE: IT IS NOT RECOMMENDED TO USE ANY OTHER STRAP OPTIONS WITH THIS
STRAP FUNCTION
OP_LOW = 1: all outputs are held LOW during power up until released by programming
OP_LOW release/set register HIGH
NOTE: Before the device is powered up, the outputs are in tri-state.
See
OP_LOW = 0: all outputs toggle normally as soon as LOCK goes HIGH (default).
Output Sleep State Select — Pin or Register Control
NOTE: OSS_SEL STRAP CANNOT BE USED IF OP_LOW =1
OSS_SEL is used in conjunction with PDB to determine the state of the outputs in Power
Down (Sleep). (See
Pixel Clock Output Strobe Edge Select — Pin or Register Control
RFB = 1, parallel interface data and control signals are strobed on the rising clock edge.
RFB = 0, parallel interface data and control signals are strobed on the falling clock edge.
Receiver Input Equalization — Pin or Register Control
(See
Oscillator Select — Pin or Register Control
(See
Spread Spectrum Clock Generation (SSCG) Range Select — Pin or Register Control
(See
Bit Mapping Backward Compatibility / DS90UR241 Options — Pin or Register Control
Normal setting to b'00. See
Power Down Mode Input
PDB = 1, Des is enabled (normal operation).
Refer to “Power Up Requirements and PDB Pin” in the Applications Information Section.
PDB = 0, Des is in power-down.
When the Des is in the power-down state, the LVCMOS output state is determined by
8. Control Registers are RESET.
Serial Control Bus Device ID Address Select — Optional
Resistor to Ground and 10 kΩ pull-up to 1.8V rail. (See
SCL requires an external pull-up resistor to V
Serial Control Bus Data Input / Output - Optional
SDA requires an external pull-up resistor to V
BIST Enable Input — Optional
BISTEN = 1, BIST is enabled
BISTEN = 0, BIST is disabled
Reserved - tie LOW
Figure 26
Table
Table 9
Table 6
5).
and
and
and
Table
Table
Figure
Table
8
10).
7).
27.
8).
(Table
11).
DDIO
DDIO
.
.
Table
12).
Table