DS90UR905QSQ/NOPB National Semiconductor, DS90UR905QSQ/NOPB Datasheet - Page 32

• Manufacturer Part Number: DS90UR905QSQ/NOPB
• Description: IC SER/DESERIAL 24BIT 48LLP
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of DS90UR905QSQ/NOPB

• Function: Serializer
• Data Rate: 1.82Gbps
• Input Type: Parallel
• Output Type: Serial
• Number Of Inputs: 24
• Number Of Outputs: 1
• Voltage - Supply: 1.71 V ~ 1.89 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 48-WFQFN, Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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Des — Control Signal Filter — Optional
The Des provides an optional Control Signal (VS, HS, DE)
filter that monitors the three video control signals and elimi-
nates any pulses that are 1 or 2 PCLKs wide. Control signals
must be 3 pixel clocks wide (in its HIGH or LOW state, re-
gardless of which state is active). This is set by the CONFIG
[1:0] or by the Control Register. This feature may be controlled
by the external pin or by Register.
Des — Low Frequency Optimization (LF_Mode)
This feature may be controlled by the external pin or by Reg-
ister.
Des — Map Select
This feature may be controlled by the external pin or by Reg-
ister.
Des — Strap Input Pins
Configuration of the device maybe done via configuration in-
put pins and the STRAP input pins, or via the Serial Control
Bus. The STRAP input pins share select parallel bus output
pins. They are used to load in configuration values during the
initial power up sequence of the device. Only a pull-up on the
pin is required when a HIGH is desired. By default the pad
has an internal pull down, and will bias Low by itself. The rec-
ommended value of the pull up is 10 kΩ to V
for Low, no pull-down is required (internal pull-down). If using
the Serial Control Bus, no pull ups are required.
Optional Serial Bus Control
Please see the following section on the optional Serial Bus
Control Interface.
Optional BIST Mode
Please see the following section on the chipset BIST mode
for details.
MAPSEL1
H
L
L
TABLE 11. Map Select Configuration
INPUTS
MAPSEL0
H or L
H
L
Bit 4, Bit 5 on LSB
DDIO
LSB 0 or 1
DEFAULT
Effect
LSB 0
; open (NC)
32
Built In Self Test (BIST)
An optional At-Speed Built In Self Test (BIST) feature sup-
ports the testing of the high-speed serial link. This is useful in
the prototype stage, equipment production, in-system test
and also for system diagnostics. In the BIST mode only a input
clock is required along with control to the Ser and Des BIS-
TEN input pins. The Ser outputs a test pattern (PRBS7) and
drives the link at speed. The Des detects the PRBS7 pattern
and monitors it for errors. A PASS output pin toggles to flag
any payloads that are received with 1 to 24 errors. Upon com-
pletion of the test, the result of the test is held on the PASS
output until reset (new BIST test or Power Down). A high on
PASS indicates NO ERRORS were detected. A Low on PASS
indicates one or more errors were detected. The duration of
the test is controlled by the pulse width applied to the Des
BISTEN pin. During the BIST duration the deserializer data
outputs toggle with a checkerboard pattern.
Inter-operability is supported between this FPD-Link II device
and all FPD-Link II generations (Gen 1/2/3) — see respective
datasheets for details on entering BIST mode and control.
Sample BIST Sequence
See
Step 1: Place the DS90UR905Q Ser in BIST Mode by setting
Ser BISTEN = H. For the DS90UR905Q Ser or DS99R421
FPD-Link II Ser BIST Mode is enabled via the BISTEN pin.
For the DS90C241 Ser or DS90UR241 Ser, BIST mode is
enetered by setting all the input data of the device to Low
state. A PCLK is required for all the Ser options. When the
Des detects the BIST mode pattern and command (DCA and
DCB code) the RGB and control signal outputs are shut off.
Step 2: Place the DS90UR906Q Des in BIST mode by setting
the BISTEN = H. The Des is now in the BIST mode and checks
the incoming serial payloads for errors. If an error in the pay-
load (1 to 24) is detected, the PASS pin will switch low for one
half of the clock period. During the BIST test, the PASS output
can be monitored and counted to determine the payload error
rate.
Step 3: To Stop the BIST mode, the Des BISTEN pin is set
Low. The Des stops checking the data and the final test result
is held on the PASS pin. If the test ran error free, the PASS
output will be High. If there was one or more errors detected,
the PASS output will be Low. The PASS output state is held
until a new BIST is run, the device is RESET, or Powered
Down. The BIST duration is user controlled by the duration of
the BISTEN signal.
Step 4: To return the link to normal operation, the Ser BISTEN
input is set Low. The Link returns to normal operation.
Figure 29
for two cases. Case 1 is error free, and Case 2 shows one
with multiple errors. In most cases it is difficult to generate
errors due to the robustness of the link (differential data trans-
mission etc.), thus they may be introduced by greatly extend-
ing the cable length, faulting the interconnect, reducing signal
condition enhancements (De-Emphasis, VODSEL, or Rx
Equalization).
Figure 28
shows the waveform diagram of a typical BIST test
for the BIST mode flow diagram.