TRC101 RFM, TRC101 Datasheet - Page 27

• Manufacturer Part Number: TRC101
• Description: RFIC TRANCEIVER MULTI-CHANNEL FS
• Manufacturer: RFM
• Series: TRCr

Specifications of TRC101

• Frequency: 300MHz ~ 1GHz
• Data Rate - Maximum: 256kbps
• Modulation Or Protocol: FSK
• Applications: General Purpose
• Power - Output: 8dBm
• Sensitivity: -105dBm
• Voltage - Supply: 2.2 V ~ 5.4 V
• Current - Receiving: 17mA
• Current - Transmitting: 28mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 16-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Memory Size: -
• Other names: 583-1093-2

Bit
15
Data Rate Setup Register
1
The Data Rate Setup Register configures:
Bit [15..8] - Command Code: These bits are the command code that is sent serially to the processor that
identifies the bits to be written to the Data Rate Setup Register.
Bit [7] – Prescaler Enable: When set this bit enables the prescaler to obtain smaller values of expected
data rates. The prescaler value is approximately 1/8.
Bit [6..0] – Data Rate Parameter Value: These bits represent the decimal value of the 7-bit parameter
used to calculate the expected data rate. To calculate the expected data rate, use the following formula:
To calculate the BITR[6..0] decimal value for a given bit rate, use the following formula:
Without the prescaler, the definable data rates range from 2.694kpbs to 344.828kbps. With the prescaler
enabled, the definable data rates range from 337 bps to 43.103kpbs.
The Slow clock recovery mode requires more accurate bit timing when setting the data rate. To calculate
the accuracy of the data rate for both Fast and Slow mode, use the following:
where N is the longest number of expected ones or zeros in the data stream, ΔBR is the difference in the
actual data rate vs. the set data rate in the transmitter, and BR is the expected data rate as set above
using BITR[6..0].
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Bit
14
1
where BITR[6..0] is the decimal value 0 to 127 and the prescaler (PRE) is ‘1’ (on) or ‘0’ (off).
where DRexp is the expected data rate and PRE is defined above.
•
•
•
Bit
13
0
Slow mode Acc = ΔBR/BR < 1/(29 * N)
Expected data rate for the receiver
Prescaler
Effects of the data rate on clock recovery
Bit
12
0
Email: [e-mail]
Bit
11
0
Bit
10
DR
1
exp
BITR[6..0] = 10000 / [29 * (1+PRE*7) * DR
Bit
9
1
(kbps) = 10000 / [29 * (BITR[6..0]+1) * (1+PRE*7)]
[POR=C623h]
Bit
8
0
PRE
Bit
7
BITR6
Bit
6
BITR5
Bit
5
Fast mode = ΔBR/BR < 3/(29 * N)
BITR4
Bit
4
exp
BITR3
] -1
Bit
3
BITR2
Bit
2
BITR1
Bit
TRC101 - 4/8/08
1
Page 27 of 42
BITR0
Bit
0