SI4420-D1-FT Silicon Laboratories Inc, SI4420-D1-FT Datasheet - Page 21

• Manufacturer Part Number: SI4420-D1-FT
• Description: IC TXRX FSK 915MHZ 5.4V 16-TSSOP
• Manufacturer: Silicon Laboratories Inc

Specifications of SI4420-D1-FT

• Package / Case: 16-TSSOP
• Frequency: 315MHz, 433MHz, 868MHz, and 915MHz
• Data Rate - Maximum: 256kbps
• Modulation Or Protocol: FSK
• Power - Output: -21dbm
• Sensitivity: -109dBm
• Voltage - Supply: 2.2 V ~ 5.4 V
• Current - Receiving: 15mA
• Current - Transmitting: 26mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Number Of Receivers: 2
• Number Of Transmitters: 2
• Wireless Frequency: 315 MHz to 915 MHz
• Interface Type: SPI
• Output Power: 4 dBm to 8 dBm
• Operating Supply Voltage: 2.2 V to 5.4 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Maximum Supply Current: 25 mA
• Minimum Operating Temperature: - 40 C
• Modulation: FSK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Applications: -
• Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1630-5

13. Low Duty-Cycle Command
With this command, Low Duty-Cycle operation can be set in order to decrease the average power consumption in receiver mode.
The time cycle is determined by the Wake-Up Timer Command.
The Duty-Cycle can be calculated by using (d6 to d0) and M. (M is parameter in a Wake-Up Timer Command.)
Duty-Cycle= (D * 2 +1) / M *100%
Bit 0 (en): Enables the Low Duty-Cycle Mode. Wake-up timer interrupt not generated in this mode.
Note: In this operation mode, bit er must be cleared and bit ew must be set in the Power Management Command.
14. Low Battery Detector and Microcontroller Clock Divider Command
The 5 bit parameter (v4 to v0) represents the value V, which defines the threshold voltage V
V
Clock divider configuration:
The low battery detector and the clock output can be enabled or disabled by bits eb and dc, respectively, using the Power Management
Command.
lb
d2
Bit
Bit
= 2.25 + V * 0.1 [V]
0
0
0
0
1
1
1
1
d1
0
0
1
1
0
0
1
1
15
15
1
1
d0
0
1
0
1
0
1
0
1
Receiver
Xtal osc.
enable
14
14
DQD
1
1
On
13
13
0
0
Frequency [MHz]
Clock Output
12
12
0
0
1.25
1.66
3.33
2.5
10
1
2
5
11
11
1
0
2.25ms
Ton
10
10
0
0
Twake-up
9
0
9
0
8
0
8
0
d6
d2
7
7
d5
d1
6
6
Ton
d4
d0
5
5
Twake-up
d3
v4
4
4
d2
v3
3
3
lb
of the detector:
d1
v2
2
2
d0
v1
1
1
2.25ms
Ton
en
v0
Twake-up
0
0
C80Eh
C000h
POR
POR
Si4420
21