SI4420-D1-FT Silicon Laboratories Inc, SI4420-D1-FT Datasheet - Page 17

• Manufacturer Part Number: SI4420-D1-FT
• Description: IC TXRX FSK 915MHZ 5.4V 16-TSSOP
• Manufacturer: Silicon Laboratories Inc

Specifications of SI4420-D1-FT

• Package / Case: 16-TSSOP
• Frequency: 315MHz, 433MHz, 868MHz, and 915MHz
• Data Rate - Maximum: 256kbps
• Modulation Or Protocol: FSK
• Power - Output: -21dbm
• Sensitivity: -109dBm
• Voltage - Supply: 2.2 V ~ 5.4 V
• Current - Receiving: 15mA
• Current - Transmitting: 26mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Number Of Receivers: 2
• Number Of Transmitters: 2
• Wireless Frequency: 315 MHz to 915 MHz
• Interface Type: SPI
• Output Power: 4 dBm to 8 dBm
• Operating Supply Voltage: 2.2 V to 5.4 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Maximum Supply Current: 25 mA
• Minimum Operating Temperature: - 40 C
• Modulation: FSK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Applications: -
• Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1630-5

Bits 2-0 (f2 to f0): DQD threshold parameter.
7. FIFO and Reset Mode Command
Bits 7-4 (f3 to f0): FIFO IT level. The FIFO generates IT when the number of received data bits reaches this level.
Bit 2 (al): Set the input of the FIFO fill start condition:
Note: Synchron pattern in microcontroller mode is 2DD4h.
Bit 1 (ff): FIFO fill will be enabled after synchron pattern reception. The FIFO fill stops when this bit is cleared.
Bit 0 (dr): Disables the highly sensitive RESET mode. If this bit is cleared, a 600 mV glitch in the power supply may cause a system reset. For
more detailed description see the Reset modes section.
Note:
Bit
To restart the synchron pattern recognition, bit 1 should be cleared and set.
15
1
Note: To let the DQD report "good signal quality" the threshold parameter should be less than 4 in the case when the bitrate is
14
SYNCHRON
1
PATTERN
close to the deviation. At higher deviation/bitrate settings higher threshold parameter can report "good signal quality" as
well.
13
0
12
0
11
1
10
0
FFIT
er**
FFOV
9
1
al
0
1
8
0
f3
7
Note:
* For details see the Configuration Setting Command
** For deatils see the Power Management Command
Synchron pattern
ef*
Always fill
al
f2
ff
6
f1
5
f0
4
3
0
FIFO_WRITE _EN
nFIFO_RESET
al
2
FIFO_LOGIC
1
ff
dr
0
CA80h
POR
Si4420
17