ADF7025BCPZ Analog Devices Inc, ADF7025BCPZ Datasheet - Page 27

• Manufacturer Part Number: ADF7025BCPZ
• Description: IC ASK/FSK TXRX 928MHZ 48-LFCSP
• Manufacturer: Analog Devices Inc

Specifications of ADF7025BCPZ

• Frequency: 431MHz ~ 464MHz, 862MHz ~ 870MHz and 902MHz ~ 928MHz
• Data Rate - Maximum: 384kbps
• Modulation Or Protocol: FSK
• Applications: Keyless Entery, Home Automation, Wireless Audio/Video
• Power - Output: -20dBm ~ 13dBm
• Sensitivity: -104dBm
• Voltage - Supply: 2.3 V ~ 3.6 V
• Current - Receiving: 19mA
• Current - Transmitting: 28mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LFCSP
• Receiving Current: 21mA
• Transmitting Current: 19.3mA
• Data Rate: 384Kbps
• Frequency Range: 431MHz To 928MHz
• Modulation Type: FSK
• Rf Ic Case Style: LFCSP
• No. Of Pins: 48
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-ADF70XXEKZ1 - KIT DEV ADF702X FOR BF533EZKITEVAL-ADF7025DBZ1 - BOARD EVAL ADF7025 902-928MHZ
• Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

SERIAL INTERFACE
The serial interface allows the user to program the eleven 32-bit
registers using a 3-wire interface (SCLK, SDATA, and SLE). It
consists of a level shifter, a 32-bit shift register, and 11 latches.
Signals should be CMOS-compatible. The serial interface is
powered by the regulator, and, therefore, is inactive when CE
is low.
Data is clocked into the register, MSB first, on the rising edge of
each clock (SCLK). Data is transferred to one of 11 latches on
the rising edge of SLE. The destination latch is determined by
the value of the four control bits (C4 to C1). These are the
bottom four LSBs, DB3 to DB0, as shown in the timing diagram
in Figure 2. Data can also be read back on the SREAD pin.
READBACK FORMAT
The readback operation is initiated by writing a valid control
word to the readback register and setting the readback-enable
bit (R7_DB8 = 1). The readback can begin after the control
word has been latched with the SLE signal. SLE must be kept
high while the data is being read out. Each active edge at the
SCLK pin clocks the readback word out successively at the
SREAD pin, as shown in Figure 38, starting with the MSB first.
The data appearing at the first clock cycle following the latch
operation must be ignored.
RSSI Readback
The RSSI readback operation yields valid results in Rx mode.
The format of the readback word is shown in Figure 38. It
comprises the RSSI level information (Bit RV1 to Bit RV7), the
current filter gain (FG1 and FG2), and the current LNA gain
(LG1 and LG2) setting. The filter and LNA gain are coded in
accordance with the definitions in Register 9—AGC Register.
The input power can be calculated from the RSSI readback
value, as outlined in the RSSI/AGC section.
BATTERY VOLTAGE/ADCIN/
TEMP. SENSOR READBACK
FILTER CAL READBACK
READBACK MODE
SILICON REVISION
RSSI READBACK
DB15
RV16
X
X
0
DB14
RV15
X
X
0
DB13
RV14
X
X
0
DB12
RV13
X
X
0
Figure 38. Readback Value Table
DB11
RV12
X
X
0
Rev. A | Page 27 of 44
DB10
RV11
LG2
X
0
RV10
DB9
LG1
X
0
READBACK VALUE
Battery Voltage ADCIN/Temperature Sensor Readback
The battery voltage is measured at Pin VDD4. The readback
information is contained in Bit RV1 to Bit RV7. This also
applies for the readback of the voltage at the ADCIN pin and
the temperature sensor. From the readback information, the
battery or ADCIN voltage can be determined using
Silicon Revision Readback
The silicon revision readback word is valid without setting any
other registers, especially directly after power-up. The silicon
revision word is coded with four quartets in BCD format. The
product code (PC) is coded with two quartets extending from
Bit RV9 to Bit RV16. The revision code (RV) is coded with one
quartet extending from Bit RV1 to Bit RV8. The product code
should read back as PC = 0x25. The current revision code
should read as RC = 0x08.
Filter Calibration Readback
The filter calibration readback word is contained in Bit RV1 to
Bit RV8 and is for diagnostic purposes only. Using the automatic
filter calibration function, accessible through Register 6, is
recommended. Before filter calibration is initiated, Decimal 32
should be read back.
DB8
FG2
RV9
X
0
V
V
BATTERY
ADCIN
DB7
FG1
RV8
RV8
X
= (ADCIN_Voltage_Readback)/42.1
DB6
RV7
RV7
RV7
RV7
= (Battery_Voltage_Readback)/21.1
DB5
RV6
RV6
RV6
RV6
DB4
RV5
RV5
RV5
RV5
DB3
RV4
RV4
RV4
RV4
DB2
RV3
RV3
RV3
RV3
DB1
RV2
RV2
RV2
RV2
DB0
RV1
RV1
RV1
RV1
ADF7025