ADF7025BCPZ Analog Devices Inc, ADF7025BCPZ Datasheet - Page 24

• Manufacturer Part Number: ADF7025BCPZ
• Description: IC ASK/FSK TXRX 928MHZ 48-LFCSP
• Manufacturer: Analog Devices Inc

Specifications of ADF7025BCPZ

• Frequency: 431MHz ~ 464MHz, 862MHz ~ 870MHz and 902MHz ~ 928MHz
• Data Rate - Maximum: 384kbps
• Modulation Or Protocol: FSK
• Applications: Keyless Entery, Home Automation, Wireless Audio/Video
• Power - Output: -20dBm ~ 13dBm
• Sensitivity: -104dBm
• Voltage - Supply: 2.3 V ~ 3.6 V
• Current - Receiving: 19mA
• Current - Transmitting: 28mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LFCSP
• Receiving Current: 21mA
• Transmitting Current: 19.3mA
• Data Rate: 384Kbps
• Frequency Range: 431MHz To 928MHz
• Modulation Type: FSK
• Rf Ic Case Style: LFCSP
• No. Of Pins: 48
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-ADF70XXEKZ1 - KIT DEV ADF702X FOR BF533EZKITEVAL-ADF7025DBZ1 - BOARD EVAL ADF7025 902-928MHZ
• Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

ADF7025
The procedure typically requires several iterations until an
acceptable compromise is reached. The successful implementation
of a combined LNA/PA matching network for the ADF7025 is
critically dependent on the availability of an accurate electrical
model for the PC board. In this context, the use of a suitable CAD
package is strongly recommended. To avoid this effort, however, a
small form-factor reference design for the ADF7025 is provided,
including matching and harmonic filter components. The design
is on a 2-layer PCB to minimize cost. Gerber files are available
on the
TRANSMIT PROTOCOL AND CODING
CONSIDERATIONS
A dc-free preamble pattern is recommended for FSK
demodulation. The recommended preamble pattern is a dc-free
pattern such as a 10101010… pattern. Preamble patterns with
longer run-length constraints such as 11001100…. can also be
used. However, this results in a longer synchronization time of
the received bit stream in the receiver.
Manchester coding can be used for the entire transmit protocol.
However, the remaining fields that follow the preamble header
do not have to use dc-free coding. For these fields, the ADF7025
can accommodate coding schemes with a run-length of up to
six bits without any performance degradation.
If longer run-length coding must be supported, the ADF7025
has several other features that can be activated. These involve a
range of programmable options that allow the envelope detector
output to be frozen after preamble acquisition.
DEVICE PROGRAMMING AFTER INITIAL POWER-UP
Table 7 lists the minimum number of writes needed to set up
the ADF7025 in either Tx or Rx mode after CE is brought high.
Additional registers can also be written to tailor the part to a
particular application, such as setting up sync byte detection.
When going from Tx to Rx or vice versa, the user needs to write
only to the N register to alter the LO by 200 kHz and to toggle
the Tx/Rx bit.
PREAMBLE
www.analog.com
Figure 33. Typical Format of a Transmit Protocol
WORD
SYNC
website.
FIELD
ID
DATA FIELD
CRC
Rev. A | Page 24 of 44
1
Table 7. Minimum Register Writes Required for Tx/Rx Setup
Mode
Tx
Rx (FSK)
Tx to Rx and Rx to Tx
Figure 36 and Figure 37 show the recommended programming
sequence and associated timing for power-up from standby
mode.
INTERFACING TO MICROCONTROLLER/DSP
Low level device drivers are available for interfacing to the
ADF7025, the ADI ADuC84x microcontroller parts, or the
Blackfin® BF53x DSPs using the hardware connections shown in
Figure 34 and Figure 35.
Register 9 should be programmed in receive mode in order to set the
recommended AGC threshold settings (low = 15, high = 79).
ADSP-BF533
ADuC84x
GPIO
RSCLK1
P3.2/INT0
DR1PRI
Figure 34. ADuC84X to ADF7025 Connection Diagram
DT1PRI
SCLOCK
MOSI
MISO
RFS1
Figure 35. BF533 to ADF7025 Connection Diagram
GND
SCK
VCC
PF5
PF6
MISO
MOSI
P3.7
P2.4
P2.5
P2.6
P2.7
SS
Registers
0
0
0
1
1
2
2
SCLK
SDATA
SREAD
SLE
TxRxCLK
TxRxDATA
INT/LOCK
CE
VCC
GND
ADF7025
TxRxDATA
RxCLK
CE
INT/LOCK
SREAD
SLE
SDATA
SCLK
4
ADF7025
6
9
1