TDA5221 Infineon Technologies, TDA5221 Datasheet - Page 18

• Manufacturer Part Number: TDA5221
• Description: RECEIVER SHR FSK/ASK SGL TSSOP28
• Manufacturer: Infineon Technologies
• Type: Receiverr

Specifications of TDA5221

• Package / Case: 28-TSSOP
• Frequency: 300MHz ~ 340MHz
• Sensitivity: -113dBm
• Data Rate - Maximum: 100 kbps
• Modulation Or Protocol: ASK, FSK
• Applications: RKE, Remote Control Systems
• Current - Receiving: 6.2mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 105°C
• Operating Frequency: 340 MHz
• Operating Supply Voltage: 5 V
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Temperature (min): -40C
• Operating Temperature (max): 105C
• Operating Temperature Classification: Industrial
• Product Depth (mm): 4.4mm
• Product Length (mm): 9.7mm
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Memory Size: -
• Lead Free Status / Rohs Status: Compliant
• Other names: SP000014343; TDA5221; TDA5221INTR; TDA5221XT

Sallen-Key low pass filter is formed. The selection of the capacitor values is described
in Section 3.2.
2.4.8
The data slicer is a fast comparator with a bandwidth of 100 kHz. This allows for a
maximum receive data rate of up to 100kBaud. The maximum achievable data rate also
depends on the IF Filter bandwidth and the local oscillator tolerance values. Both inputs
are accessible. The output delivers a digital data signal (CMOS-like levels) for
subsequent circuits. A self-adjusting slicer-threshold on pin 20 its generated by a RC-
term. In ASK-mode alternatively a scaled value of the voltage at the PDO-output (approx.
87%) can be used as the slicer-threshold as shown in Table 4. The data slicer threshold
generation alternatives are described in more detail in Section 3.5.
Table 4
SSEL
X
High
Low
2.4.9
The peak detector generates a DC voltage which is proportional to the peak value of the
receive data signal. A capacitor is necessary. The input is connected to the output of the
RSSI-output of the Limiter, the output is connected to the PDO pin (Pin 26). This output
can be used as an indicator for the received signal strength to use in wake-up circuits
and as a reference for the data slicer in ASK mode. Note that the RSSI level is also
output in case of FSK mode.
2.4.10
A Bandgap Reference Circuit provides a temperature stable reference voltage for the
device. A power down mode is available to switch off all subcircuits which is controlled
by the PWDN pin (Pin 27) as shown in the following table. The supply current drawn in
this case is typically 50nA.
Table 5
PDWN
Open or tied to ground
Tied to Vs
Preliminary Specification
Data Slicer
Peak Detector
Bandgap Reference Circuitry
SSEL Pin Operating States
PDWN Pin Operating States
MSEL
Low
High
High
18
Operating State
Powerdown Mode
Receiver On
Selected Slicing Level (SL)
external SL on Pin 20 (RC-term, e.g.)
external SL on Pin 20 (RC-term, e.g.)
87% of PDO-output (approx.)
Functional Description
V 1.1, 2004-10-20
TDA 5221