LTC4401-1ES6#TR Linear Technology, LTC4401-1ES6#TR Datasheet - Page 8

• Manufacturer Part Number: LTC4401-1ES6#TR
• Description: IC RF POWER CONTROLLER TSOT23-6
• Manufacturer: Linear Technology

Specifications of LTC4401-1ES6#TR

• Rf Type: Cellular, GSM, GPRS, PCS, Wireless Modem, TDMA
• Frequency: 300MHz ~ 2.7GHz
• Features: Single Output
• Package / Case: TSOT-23-6, TSOT-6
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: LTC4401-1ES6TR; LTC44011ES6TR

LTC4401-1/LTC4401-2
APPLICATIO S I FOR ATIO
Enable: When SHDN is asserted high the part will auto-
matically calibrate out all offsets. This takes <10 s and is
controlled by an internal delay circuit. After 10 s V
will step up to the starting voltage of 450mV. The user can
then apply the ramp signal. The user should wait 12 s after
SHDN has been asserted high before applying the ramp.
The DAC should be settled 2 s after asserting SHDN high.
General Layout Considerations
The LTC4401-X should be placed near the directional
coupler. The feedback signal line to the RF pin should be
a 50
short line.
External Termination
The LTC4401-X has an internal 250 termination resistor
at the RF pin. If a directional coupler is used, it is recom-
mended that an external 68
connected between the RF coupling capacitor (33pF), and
ground at the side connected to the directional coupler.
Termination components should be placed adjacent to the
LTC4401-X.
8
V
T1: LTC4401-X COMES OUT OF SHUTDOWN 12 s PRIOR TO BURST
T2: INTERNAL TIMER COMPLETES AUTOZERO CORRECTION, <10 s
T3: BASEBAND CONTROLLER STARTS RF POWER RAMP UP AT 12 s AFTER
T4: BASEBAND CONTROLLER COMPLETES RAMP UP
T5: BASEBAND CONTROLLER STARTS RF POWER RAMP DOWN AT END OF BURST
T6: LTC4401-X RETURNS TO SHUTDOWN MODE BETWEEN BURSTS
T7: BSEL CHANGE PRIOR TO SHDN, 0ns TYPICAL (LTC4401-2 ONLY)
T8: BSEL CHANGE AFTER TO SHDN, 0ns TYPICAL (LTC4401-2 ONLY)
SHDN
BSEL
PCA/B
PCTL
SHDN IS ASSERTED HIGH
transmission line with optional termination or a
T1
(LTC4401-2 ONLY)
10 s
T7
T2 T3
2 s
LTC4401-X Timing Diagram
28 s
V
START
U
T4
U
543 s
termination resistor be
W
T5
28 s
U
T6
4400 TA02
PCA/B
T8
Power Ramp Profiles
The external voltage gain associated with the RF channel
can vary significantly between RF power amplifier types.
The LTC4401-X frequency compensation has been
optimized to be stable with several different power ampli-
fiers and manufacturers. This frequency compensation
generally defines the loop dynamics that impact the power/
time response and possibly (slow loops) the power ramp
sidebands. The LTC4401-X operates open loop until an RF
voltage appears at the RF pin, at which time the loop closes
and the output power follows the DAC profile. The RF
power amplifier will require a certain control voltage level
(threshold) before an RF output signal is produced. The
LTC4401-X V
threshold voltage in order to meet the power/time profile.
To reduce this time, the LTC4401-X starts at 450mV.
However, at very low power levels the PCTL input signal is
small, and the V
onds to reach the RF power amplifier threshold voltage. To
reduce this time, it may be necessary to apply a positive
pulse at the start of the ramp to quickly bring the V
output to the threshold voltage. This can generally be
achieved with DAC programming. The magnitude of the
pulse is dependent on the RF amplifier characteristics.
Power ramp sidebands and power/time are also a factor
when ramping to zero power. When the power is ramped
down the loop will eventually open at power levels below
the LTC4401-X detector threshold. The LTC4401-X will
then go open loop and the output voltage at V
stop falling. If this voltage is high enough to produce RF
output power, the power/time or power ramp sidebands
may not meet specification. This problem can be avoided
by starting the DAC ramp from 200mV (Figure 1). At the
end of the cycle, the DAC can be ramped down to 0mV.
This applies a negative signal to the LTC4401-X thereby
ensuring that the V
200mV ramp step must be applied < 2 s after SHDN is
asserted high to allow the autozero to cancel the step. Slow
DAC rise times will extend this time by the additional RC
time constants which may require that the DAC is enabled
and settled prior to SHDN asserted high.
PCA/B
PCA/B
output(s) must quickly rise to this
PCA/B
output may take several microsec-
output will ramp to 0V. The
PCA/B
PCA/B
4401fa
will