AD6652BBC Analog Devices Inc, AD6652BBC Datasheet - Page 64

• Manufacturer Part Number: AD6652BBC
• Description: IC IF TO BASEBAND RCVR 256CSPBGA
• Manufacturer: Analog Devices Inc

Specifications of AD6652BBC

• Function: IF to Baseband Receiver
• Frequency: 200MHz
• Rf Type: Cellular, AMPS, CDMA, CDMA2000, UMTS, W-CDMA
• Secondary Attributes: Sample Rates up to 65MSPS
• Package / Case: 256-CSPBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

AD6652
Table 28. M
Channel Addre
00
01
02
03
04
05
06
07
OUTPUT PORT CONTROL REGISTERS
This g
indivi
ma
outpu
a
fo
guidin
deto
a
T
5 o
hig
th
co
0x00–
Res
0x0
LHB is t
wide
th
sh
fr
nu
B
in
F
prev
st
n
th
u
a
st
re two outp t ports, A and B, the data must e funneled fr
nd so on) before the output port is selected
nd Bit 1. The data is then propagated to the LHB and AGC
o access th output port registers for Outpu orts A and , Bit
igure 64. If it 3 is low, the interleave stage is shut down a
eeded and ower conservation is desired. W en Bit 3 is h
p to four D C channels according to the tr th table of Bi 2
it 3, the LHB A enable bit, acts as an on/off
om the fin AGC stage, so that they do no et lost amon
ages. This condition is desirable when the t ree stages are
ages with bypass opportunities included.
ur channe down to two. These registers a
terleave st e, half-band filter, and the AGC stage. See
e address t the correct output port registe
e interleaving stage as well as the half-band filter stage, as
own in Fi
e interleav tage is active and works to int eave the dat of
mplete lis
merous A C control elements.
nage data nterleaving, 2× interpolation, A C functions,
f Externa
h. The ch nnel address register (CAR) is t en written wi
erved. Al its should be written logic low
8: LHB
uring th
ents any
ly accep d symbol for interpolation. This register incl des
dual channels have processed the incoming data. The
t port signment, and output port setu . Because the
roup o registers is dedicated to data management af
g the
0x07: Reserved
he acronym for interpolating half-band, with L bei
gur
e
tin
A Control Registe
as
ls
da
al
ag
p
emory Ma
l A
G
e s
u
e data through o
a
l b
D
o
te
B
f
further propag
i
ta directly to the proper outpu
g and brief description of all r isters.
ddress 3 (the sleep register) m st be written logic
e 64. These two stages are con olled separa
ss
Register
Lower Threshold A
Upper Threshold A
Dwell Time A
Gain Range A Control
Lower Threshold B
Upper Threshold B
Dwell Time B
Gain Range B Control Register
p for Input Port Control Registers
ation of data to t
ther post-filteri
r
.
t g
re resp
ng s
r. S
eg
he re
h
erl
u
Reg
b
t p
t P
swi
.
tr
p
u
h
G
h
ort(s) or
ee Table 29 for a
tch for the
ister
tages (AG
maining
onsible for
C,
igh,
ter
B
tely
nd
ng a
t
om
u
g th
y
a
re
th
not
Bit
10
10
20
5
10
10
20
5
Rev. 0 | Page 64 of 76
e
Wid
th
B
table
Bit 0, the bypass bit,
stage to bypass the h
the AGC s
a
m
chip rate.
When Bit 0 is low, data from the interleave stage is passed
through
r
ti
0x09: LHB B Control Register
S
leaved. Ch
e
0x0A: AGC A Control Register
Bits 7–5 define the o
word can be 4 to 8, 10,
o
m
Bit 4
When this bit is 0, t
level; when this bit i
clipping e
d
Bits 3–1 are u
The CIC decimator filter in the AGC can be directly synchro-
nized to an e
A
a
nized to a Rake receiver.
ate. The maximum outpu
re still interleaved, but th
nable bit.
nd filtering. This wa
ame as LHB A, except that only t
btain different output w
etails about these two m
its 2 and 1 choose whic
mes the chip rate.
GC outputs an update sam
aximum data rate from this c
emory map, 0x0A.
Co
9–0:
9–0:
19–0:
4:
3:
2–0:
9–0:
9–0:
19–0:
4:
3:
2–0:
mments
of this register sets the mode of operation for the AGC.
for these bits is shown in Table 29.
the half-band filter and undergoes a 2× interpolation
rror. See the Automatic Gain Control section for
tage without interpolation. The channel data streams
annels are selected using only Bit 1; Bit 2 is the LHB B
Lower threshold for Input A
Upper threshold for Input A
Minimum time below Lower Threshold A
Output polarity LIA and LIA
(0) Reserved
Linearization hold-off register
Lower threshold for Input B
Upper threshold for Input B
Minimum time below Lower Threshold B
Output polar
(0) Reserved
Linearization hold-off register
xternally generated signal. When synchronized, the
sed to configure the synchronization of the AGC.
he AGC tracks to maintain the output signal
s 1, the AGC tracks to maintain a constant
when high, directs data from the interleave
alf-band filter stage and proceed directly to
utput word length of the AGC. The output
y, the AGC gain changes can be synchro-
12, or 16 bits wide. The truth table to
h channels are interleaved. The truth
ity LIB and LIB
ord lengths is given in the Table 29
odes.
ey are not filtered or interpolated. The
t data rate of the half-band is four
ple for the AGC error calculation
onfiguration is two times the
wo channels can be inter-