AD6652BBC Analog Devices Inc, AD6652BBC Datasheet - Page 60

• Manufacturer Part Number: AD6652BBC
• Description: IC IF TO BASEBAND RCVR 256CSPBGA
• Manufacturer: Analog Devices Inc

Specifications of AD6652BBC

• Function: IF to Baseband Receiver
• Frequency: 200MHz
• Rf Type: Cellular, AMPS, CDMA, CDMA2000, UMTS, W-CDMA
• Secondary Attributes: Sample Rates up to 65MSPS
• Package / Case: 256-CSPBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

AD6652
Channel Address
A4
A5
A6
A7
A8
A9
0x87: NCO Phase Offset Register
This register represents a 16-bit phase offset to the NCO. It can
be interpreted as values ranging from 0 to just under 2π. The
16-bit phase offset is added t
phase accumulator to a
used to compute the amplitude value.
0x88: NCO Control Register
This 9-bit register controls features of the NCO and the
channel. The bits are defined in this section. For details, see the
Numerically Controlled Oscillator section.
Bits 8–7 of this register choose which one of the four
Pin_SYNC pins (A, B, C, or D) is used by the channel to initiate
channel start and frequency hop functions. These bits can also
be used to make timing adjustments to a channel.
Pin_Sync.
Table 25. Bit Logic States for Sync Pins
0x88:8
0
0
1
1
Bit 6 of this register defines which ADC channel, A or B, is used
by the DDC channel being programmed. If this bit is low, then
I
Bits 5–4 are reserved and must be written logic low.
Table 25 shows the bit logic state needed to select a partic
nput Port A selected; if this bit is high, Input Port B is selected.
0x88:7
0
1
0
1
Register
RCF Control Register
BIST Signature for I Path
BIST Signature for Q Path
BIST Outputs to Accumulate
RAM BIST Control Register
Output Control Register
rrive at the final phase angle number
o the 16 MSBs of the 32-bit NCO
Sync Pin Selected
A
B
C
D
ular
Rev. 0 | Page 60 of 76
Bit Wid
11
16
16
20
3
10
th
Bit 3 determines whether or not the phase accumulator of th
NCO is cleared when a hop occurs. The hop can originate fro
either Pin_SYNC or Soft_SYNC. When this bit is set to 0, the
hop is phase-continuous and the accumulator is not cle
When this bit is set to 1, the accumulator is cleared to 0 before
begins accumulating the new frequency word. This is appropri
ate when multiple channels are hopping from different fr
cies to a common frequency.
Bits 2–1 control whether or not the phas
functions of the NCO are activated. The
determined by the system constraints. See the Numericall
Controlled Oscillator section for more information on the use
of dither. As usual, a logic high activates the function.
Bit 0 of this register allows the NCO frequency translation
to be bypassed. When this occurs, the data from Input Port A is
passed down the I pa
Port B is passed down the Q path of the channel. This allo
real filter to be performed on baseband I and Q data.
Ox89–0x8F: Unused
Unused.
0x90: rCIC2 Decimation − 1 (M
This register sets the decimation in the rCIC2 filter. The va
written to this reg
d
interpolation of the channel. The decimation must always be
greater than the interpolation.
ecimation can range from 1 to 4096, depending upon the
10:
2:
Comments
9:
8:
7:
6:
5-4:
3-0:
BIST-I
BIST-Q
19-0:
1:
0:
9:
5:
4-0:
ister is the decimation minus one. The rCIC2
RCF bypass BIST
RCF input select (own 0, other 1)
Program RAM bank 1/0
Use common exponent
Force output scale
Output format
1x: Floating poi
01: Floating
00: Fixed point
Output scale
Number of outputs (counter value read)
D-RAM fail/pass
C-RAM fail/
RAM BIST enable
Map RCF data to BIST registers
Output format
1: 16-bit I and 16-bit Q
0: 12-bit
Reserved, write to Logic 0
th of the channel and the data from Input
I and 12-bit Q
pass
point 8 + 4
nt 12 + 4
rCIC2
− 1)
e and amplitude dither
use of these features is
ared.
equen-
y
ws a
stage
lue
e
m
-
it